* [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen
@ 2017-09-05 9:32 Yi Sun
2017-09-05 9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
` (14 more replies)
0 siblings, 15 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
Hi, all,
We plan to bring a new PSR (Platform Shared Resource) feature called
Intel Memory Bandwidth Allocation (MBA) to Xen.
Besides the MBA enabling, we change some interfaces to make them more
general but not only for CAT.
Any comments are welcome!
You can find this series at:
https://github.com/yisun-git/xen_mba mba_v3-1
This v3 series bases on below two patches which are being reviewed now. I may
take one or two weeks leave from tomorrow. So I submit v3 before below patches
are merged and hope not to delay the review progress. Sorry for that.
[PATCH v3 1/2] tools: use '__i386__' and '__x86_64__' to replace PSR macros
https://lists.xen.org/archives/html/xen-devel/2017-09/msg00229.html
[PATCH v3 2/2] tools: change the type of '*nr' in 'libxl_psr_cat_get_info'
https://lists.xen.org/archives/html/xen-devel/2017-09/msg00230.html
---
Acked and Reviewed list before V3:
a - Acked-by
r - Reviewed-by
ar patch 2 - Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
r patch 3 - x86: rename 'cbm_type' to 'psr_type' to make it general
r patch 6 - x86: implement get value interface for MBA
ar patch 12 - tools: rename 'xc_psr_cat_type' to 'xc_psr_type'
a patch 13 - tools: implement new generic get value interface and MBA get value command
a patch 15 - docs: add MBA description in docs
---
V3 change list:
Patch 1:
- remove 'closed-loop' related description.
(suggested by Roger Pau Monné)
- explain 'linear' and 'non-linear' before mentioning them.
(suggested by Roger Pau Monné)
- adjust desription of 'psr-mba-set'.
(suggested by Roger Pau Monné)
- explain 'MBA_MAX'.
(suggested by Roger Pau Monné)
- remove 'n<64'.
(suggested by Roger Pau Monné)
- fix some wordings.
(suggested by Roger Pau Monné)
- add context in 'Testing' part to make things more clear.
(suggested by Roger Pau Monné)
Patch 2:
- remove 'op/OP' from names and modify some names from 'PSR_CAT' to
'PSR_ALLOC'.
(suggested by Roger Pau Monné)
Patch 3:
- replace 'psr_val_type' to 'psr_type' and remove '_VAL' from the enum
items.
(suggested by Roger Pau Monné)
Patch 4:
- replace 'psr_val_type' to 'psr_type'. Also, change 'PSR_VAL_TYPE_MBA' to
'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
- replace 'MBA_LINEAR' to 'MBA_LINEAR_MASK' to make the name more clear.
(suggested by Roger Pau Monné)
- replase 'cat_info'/'mba_info' to 'cat'/'mba' to make the names shorter.
(suggested by Roger Pau Monné)
- change type of 'linear' to 'bool'.
(suggested by Roger Pau Monné)
- make format string of printf in one line.
(suggested by Roger Pau Monné)
Patch 5:
- replace 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
Patch 6:
- change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
Patch 7:
- modify commit message to make it clear.
(suggested by Roger Pau Monné)
- modify functionality of 'check_val' to make it simple to only check value.
Change the last parameter type from 'unsigned long *' to 'unsigned long'.
(suggested by Roger Pau Monné)
- call rdmsrl to get value just written into MSR for MBA. Because HW can
automatically change input value to what it wants.
(suggested by Roger Pau Monné)
- change type of 'write_msr' to 'uint32_t' to return the value actually
written into MSR. Then, change 'do_write_psr_msrs' to set the returned
value into 'cos_reg_val[]'
- move the declaration of 'j' into loop in 'do_write_psr_msrs'.
(suggested by Roger Pau Monné)
- change 'mba_info' to 'mba'.
(suggested by Roger Pau Monné)
- change 'cat_info' to 'cat'.
(suggested by Roger Pau Monné)
- rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
from name.
(suggested by Roger Pau Monné)
- change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
Patch 8:
- change 'LIBXL_HAVE_PSR_MBA' to 'LIBXL_HAVE_PSR_GENERIC'.
(suggested by Roger Pau Monné)
- 'typedef enum libxl_psr_cbm_type libxl_psr_type;' in libxl.h.
(suggested by Roger Pau Monné and Wei Liu)
- change 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly defined
interfaces.
(suggested by Roger Pau Monné)
Patch 9:
- rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
from name.
(suggested by Roger Pau Monné)
- remove 'info' from 'xc_cat_info' and 'xc_mba_info'.
(suggested by Roger Pau Monné)
- set errno in 'xc_psr_get_hw_info'.
(suggested by Roger Pau Monné)
- remove 'inline'.
(suggested by Roger Pau Monné)
- remove 'psr' from 'libxl__psr_feat_type_to_libxc_psr_feat_type' to make
function name shorter.
(suggested by Roger Pau Monné)
- check 'xc_type' in 'libxl_psr_cat_get_info'.
(suggested by Roger Pau Monné)
Patch 10:
- remove casting.
(suggested by Roger Pau Monné)
- remove inline.
(suggested by Roger Pau Monné)
- change 'libxc__psr_hw_info_to_libxl_psr_hw_info' to
'libxl__xc_hw_info_to_libxl_hw_info'.
(suggested by Roger Pau Monné)
- remove '_hw' from parameter names.
(suggested by Roger Pau Monné)
- change some 'LOGE' to 'LOG'.
(suggested by Roger Pau Monné)
- check returned 'xc_type' and remove redundant 'lvl' check.
(suggested by Roger Pau Monné)
Patch 11:
- change the format string of printf in 'psr_mba_hwinfo'.
(suggested by Roger Pau Monné)
- add 'const' for 'opts[]' in 'main_psr_hwinfo'.
(suggested by Roger Pau Monné)
Patch 12:
- change 'xc_psr_val_type' to 'xc_psr_type'.
(suggested by Roger Pau Monné)
Patch 13:
- replace 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly defined
interfaces.
(suggested by Roger Pau Monné)
Patch 14:
- add 'const' for 'opts[]' in 'main_psr_mba_set'.
(suggested by Roger Pau Monné)
- replace 'libxl_psr_cbm_type' to 'libxl_psr_type' for newly defined
interfaces.
(suggested by Roger Pau Monné)
Yi Sun (15):
docs: create Memory Bandwidth Allocation (MBA) feature document
Rename PSR sysctl/domctl interfaces and xsm policy to make them be
general
x86: rename 'cbm_type' to 'psr_type' to make it general
x86: implement data structure and CPU init flow for MBA
x86: implement get hw info flow for MBA
x86: implement get value interface for MBA
x86: implement set value flow for MBA
tools: create general interfaces to support psr allocation features
tools: implement the new libxc get hw info interface
tools: implement the new libxl get hw info interface
tools: implement the new xl get hw info interface
tools: rename 'xc_psr_cat_type' to 'xc_psr_type'
tools: implement new generic get value interface and MBA get value
command
tools: implement new generic set value interface and MBA set value
command
docs: add MBA description in docs
docs/features/intel_psr_mba.pandoc | 283 +++++++++++++++++++++++++++++
docs/man/xl.pod.1.in | 34 ++++
docs/misc/xl-psr.markdown | 63 +++++++
tools/flask/policy/modules/dom0.te | 4 +-
tools/libxc/include/xenctrl.h | 47 +++--
tools/libxc/xc_psr.c | 107 +++++++----
tools/libxl/libxl.h | 33 ++++
tools/libxl/libxl_psr.c | 237 ++++++++++++++++++++-----
tools/libxl/libxl_types.idl | 22 +++
tools/xl/xl.h | 2 +
tools/xl/xl_cmdtable.c | 12 ++
tools/xl/xl_psr.c | 280 +++++++++++++++++++++++------
xen/arch/x86/domctl.c | 81 +++++----
xen/arch/x86/psr.c | 345 ++++++++++++++++++++++++++----------
xen/arch/x86/sysctl.c | 51 ++++--
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 22 ++-
xen/include/public/domctl.h | 30 ++--
xen/include/public/sysctl.h | 26 ++-
xen/xsm/flask/hooks.c | 8 +-
xen/xsm/flask/policy/access_vectors | 8 +-
21 files changed, 1357 insertions(+), 339 deletions(-)
create mode 100644 docs/features/intel_psr_mba.pandoc
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-18 17:16 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
` (13 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch creates MBA feature document in doc/features/. It describes
key points to implement MBA which is described in details in Intel SDM
"Introduction to Memory Bandwidth Allocation".
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- remove 'closed-loop' related description.
(suggested by Roger Pau Monné)
- explain 'linear' and 'non-linear' before mentioning them.
(suggested by Roger Pau Monné)
- adjust desription of 'psr-mba-set'.
(suggested by Roger Pau Monné)
- explain 'MBA_MAX'.
(suggested by Roger Pau Monné)
- remove 'n<64'.
(suggested by Roger Pau Monné)
- fix some wordings.
(suggested by Roger Pau Monné)
- add context in 'Testing' part to make things more clear.
(suggested by Roger Pau Monné)
v2:
- declare 'HW' in Terminology.
(suggested by Chao Peng)
- replace 'COS ID of VCPU' to 'COS ID of domain'.
(suggested by Chao Peng)
- replace 'COS register' to 'Thrtl MSR'.
(suggested by Chao Peng)
- add description for 'psr-mba-show' to state that the decimal value is
shown for linear mode but hexadecimal value is shown for non-linear mode.
(suggested by Chao Peng)
- remove content in 'Areas for improvement'.
(suggested by Chao Peng)
- use '<>' to specify mandatory argument to a command.
(suggested by Wei Liu)
v1:
- remove a special character to avoid the error when building pandoc.
---
docs/features/intel_psr_mba.pandoc | 283 +++++++++++++++++++++++++++++++++++++
1 file changed, 283 insertions(+)
create mode 100644 docs/features/intel_psr_mba.pandoc
diff --git a/docs/features/intel_psr_mba.pandoc b/docs/features/intel_psr_mba.pandoc
new file mode 100644
index 0000000..693ef45
--- /dev/null
+++ b/docs/features/intel_psr_mba.pandoc
@@ -0,0 +1,283 @@
+% Intel Memory Bandwidth Allocation (MBA) Feature
+% Revision 1.5
+
+\clearpage
+
+# Basics
+
+---------------- ----------------------------------------------------
+ Status: **Tech Preview**
+
+Architecture(s): Intel x86
+
+ Component(s): Hypervisor, toolstack
+
+ Hardware: MBA is supported on Skylake Server and beyond
+---------------- ----------------------------------------------------
+
+# Terminology
+
+* CAT Cache Allocation Technology
+* CBM Capacity BitMasks
+* CDP Code and Data Prioritization
+* COS/CLOS Class of Service
+* HW Hardware
+* MBA Memory Bandwidth Allocation
+* MSRs Machine Specific Registers
+* PSR Intel Platform Shared Resource
+* THRTL Throttle value or delay value
+
+# Overview
+
+The Memory Bandwidth Allocation (MBA) feature provides indirect and approximate
+control over memory bandwidth available per-core. This feature provides OS/
+hypervisor the ability to slow misbehaving apps/domains by using a credit-based
+throttling mechanism.
+
+# User details
+
+* Feature Enabling:
+
+ Add "psr=mba" to boot line parameter to enable MBA feature.
+
+* xl interfaces:
+
+ 1. `psr-mba-show [domain-id]`:
+
+ Show memory bandwidth throttling for domain. Under different modes, it
+ shows different type of data.
+
+ There are two modes:
+ Linear mode: the response of throttling value is linear.
+ Non-linear mode: the response of throttling value is non-linear.
+
+ For linear mode, it shows the decimal value. For non-linear mode, it shows
+ hexadecimal value.
+
+ 2. `psr-mba-set [OPTIONS] <domain-id> <throttling>`:
+
+ Set memory bandwidth throttling for domain.
+
+ Options:
+ '-s': Specify the socket to process, otherwise all sockets are processed.
+
+ Throttling value set in register implies the approximate amount of delaying
+ the traffic between core and memory. The higher throttling value results in
+ lower bandwidth. The max throttling value (MBA_MAX) supported can be got
+ through CPUID.
+
+ Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
+ if the MBA_MAX value is 90, the input precision is 10%. Values not an even
+ multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
+ delay applied) by HW automatically.
+
+ Non-linear mode: input delay values are powers-of-two from zero to the
+ MBA_MAX value from CPUID. In this case any values not a power of two will
+ be rounded down the next nearest power of two by HW automatically.
+
+# Technical details
+
+MBA is a member of Intel PSR features, it shares the base PSR infrastructure
+in Xen.
+
+## Hardware perspective
+
+ MBA defines a range of MSRs to support specifying a delay value (Thrtl) per
+ COS, with details below.
+
+ ```
+ +----------------------------+----------------+
+ | MSR (per socket) | Address |
+ +----------------------------+----------------+
+ | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
+ +----------------------------+----------------+
+ | ... | ... |
+ +----------------------------+----------------+
+ | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n |
+ +----------------------------+----------------+
+ ```
+
+ When context switch happens, the COS ID of domain is written to per-thread MSR
+ `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation according
+ to the throttling value stored in the Thrtl MSR register.
+
+## The relationship between MBA and CAT/CDP
+
+ Generally speaking, MBA is completely independent of CAT/CDP, and any
+ combination may be applied at any time, e.g. enabling MBA with CAT
+ disabled.
+
+ But it needs to be noticed that MBA shares COS infrastructure with CAT,
+ although MBA is enumerated by different CPUID leaf from CAT (which
+ indicates that the max COS of MBA may be different from CAT). In some
+ cases, a domain is permitted to have a COS that is beyond one (or more)
+ of PSR features but within the others. For instance, let's assume the max
+ COS of MBA is 8 but the max COS of L3 CAT is 16, when a domain is assigned
+ 9 as COS, the L3 CAT CBM associated to COS 9 would be enforced, but for MBA,
+ the HW works as default value is set since COS 9 is beyond the max COS (8)
+ of MBA.
+
+## Design Overview
+
+* Core COS/Thrtl association
+
+ When enforcing Memory Bandwidth Allocation, all cores of domains have
+ the same default Thrtl MSR (COS0) which stores the same Thrtl (0). The
+ default Thrtl MSR is used only in hypervisor and is transparent to tool stack
+ and user.
+
+ System administrators can change PSR allocation policy at runtime by
+ using the tool stack. Since MBA shares COS ID with CAT/CDP, a COS ID
+ corresponds to a 2-tuple, like [CBM, Thrtl] with only-CAT enabled, when CDP
+ is enabled, the COS ID corresponds to a 3-tuple, like [Code_CBM, Data_CBM,
+ Thrtl]. If neither CAT nor CDP is enabled, things are easier, since one COS
+ ID corresponds to one Thrtl.
+
+* VCPU schedule
+
+ This part reuses CAT COS infrastructure.
+
+* Multi-sockets
+
+ Different sockets may have different MBA ability (like max COS)
+ although it is consistent on the same socket. So the capability
+ of per-socket MBA is specified.
+
+ This part reuses CAT COS infrastructure.
+
+## Implementation Description
+
+* Hypervisor interfaces:
+
+ 1. Boot line param: "psr=mba" to enable the feature.
+
+ 2. SYSCTL:
+ - XEN_SYSCTL_PSR_MBA_get_info: Get system MBA information.
+
+ 3. DOMCTL:
+ - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get throttling for a domain.
+ - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set throttling for a domain.
+
+* xl interfaces:
+
+ 1. psr-mba-show [domain-id]
+ Show system/domain runtime MBA throttling value. For linear mode,
+ it shows the decimal value. For non-linear mode, it shows hexadecimal
+ value.
+ => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
+
+ 2. psr-mba-set [OPTIONS] <domain-id> <throttling>
+ Set bandwidth throttling for a domain.
+ => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
+
+ 3. psr-hwinfo
+ Show PSR HW information, including L3 CAT/CDP/L2 CAT/MBA.
+ => XEN_SYSCTL_PSR_MBA_get_info
+
+* Key data structure:
+
+ 1. Feature HW info
+
+ ```
+ struct {
+ unsigned int thrtl_max;
+ bool linear;
+ } mba;
+
+ - Member `thrtl_max`
+
+ `thrtl_max` is the max throttling value to be set, i.e. MBA_MAX.
+
+ - Member `linear`
+
+ `linear` means the response of delay value is linear or not.
+
+ As mentioned above, MBA is a member of Intel PSR features, it would
+ share the base PSR infrastructure in Xen. For example, the 'cos_max'
+ is a common HW property for all features. So, for other data structure
+ details, please refer 'intel_psr_cat_cdp.pandoc'.
+
+# Limitations
+
+MBA can only work on HW which enables it (check by CPUID).
+
+# Testing
+
+We can execute these commands to verify MBA on different HWs supporting them.
+
+For example:
+ 1. User can get the MBA hardware info through 'psr-hwinfo' command. From
+ result, user can know if this hardware works under linear mode or non-
+ linear mode, the max throttling value (MBA_MAX) and so on.
+
+ root@:~$ xl psr-hwinfo --mba
+ Memory Bandwidth Allocation (MBA):
+ Socket ID : 0
+ Linear Mode : Enabled
+ Maximum COS : 7
+ Maximum Throttling Value: 90
+ Default Throttling Value: 0
+
+ 2. Then, user can set a throttling value to a domain. For example, set '0xa',
+ i.e 10% delay.
+
+ root@:~$ xl psr-mba-set 1 0xa
+
+ 3. User can check the current configuration of the domain through
+ 'psr-mab-show'. For linear mode, the decimal value is shown.
+
+ root@:~$ xl psr-mba-show 1
+ Socket ID : 0
+ Default THRTL : 0
+ ID NAME THRTL
+ 1 ubuntu14 10
+
+# Areas for improvement
+
+N/A
+
+# Known issues
+
+N/A
+
+# References
+
+"INTEL RESOURCE DIRECTOR TECHNOLOGY (INTEL RDT) ALLOCATION FEATURES" [Intel 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
+
+# History
+
+------------------------------------------------------------------------
+Date Revision Version Notes
+---------- -------- -------- -------------------------------------------
+2017-01-10 1.0 Xen 4.9 Design document written
+2017-07-10 1.1 Xen 4.10 Changes:
+ 1. Modify data structure according to latest
+ codes;
+ 2. Add content for 'Areas for improvement';
+ 3. Other minor changes.
+2017-08-09 1.2 Xen 4.10 Changes:
+ 1. Remove a special character to avoid error when
+ building pandoc.
+2017-08-15 1.3 Xen 4.10 Changes:
+ 1. Add terminology 'HW'.
+ 2. Change 'COS ID of VCPU' to 'COS ID of domain'.
+ 3. Change 'COS register' to 'Thrtl MSR'.
+ 4. Explain the value shown for 'psr-mba-show' under
+ different modes.
+ 5. Remove content in 'Areas for improvement'.
+2017-08-16 1.4 Xen 4.10 Changes:
+ 1. Add '<>' for mandatory argument.
+2017-08-30 1.5 Xen 4.10 Changes:
+ 1. Modify words in 'Overview' to make it easier to
+ understand.
+ 2. Explain 'linear/non-linear' modes before mention
+ them.
+ 3. Explain throttling value more accurate.
+ 4. Explain 'MBA_MAX'.
+ 5. Correct some words in 'Design Overview'.
+ 6. Change 'mba_info' to 'mba' according to code
+ changes. Also, modify contents of it.
+ 7. Add context in 'Testing' part to make things
+ more clear.
+ 8. Remove 'n<64' to avoid out-of-sync.
+---------- -------- -------- -------------------------------------------
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-09-05 9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 8:03 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
` (12 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch renames PSR sysctl/domctl interfaces and related xsm policy to
make them be general for all resource allocation features but not only
for CAT. Then, we can resuse the interfaces for all allocation features.
Basically, it changes 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove
'op/OP'. E.g.:
1. psr_cat_op -> psr_alloc
2. XEN_DOMCTL_psr_cat_op -> XEN_DOMCTL_psr_alloc
3. XEN_SYSCTL_psr_cat_op -> XEN_SYSCTL_psr_alloc
The sysctl/domctl version numbers are bumped.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Acked-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
---
v3:
- remove 'op/OP' from names and modify some names from 'PSR_CAT' to
'PSR_ALLOC'.
(suggested by Roger Pau Monné)
v1:
- add description about what to be changed in commit message.
(suggested by Wei Liu)
- bump sysctl/domctl version numbers.
(suggested by Wei Liu)
---
tools/flask/policy/modules/dom0.te | 4 +--
tools/libxc/xc_psr.c | 52 ++++++++++++++++++-------------------
xen/arch/x86/domctl.c | 52 ++++++++++++++++++-------------------
xen/arch/x86/psr.c | 2 +-
xen/arch/x86/sysctl.c | 28 ++++++++++----------
xen/include/public/domctl.h | 28 ++++++++++----------
xen/include/public/sysctl.h | 18 ++++++-------
xen/xsm/flask/hooks.c | 8 +++---
xen/xsm/flask/policy/access_vectors | 8 +++---
9 files changed, 100 insertions(+), 100 deletions(-)
diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index d0a4d91..3dc9834 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -14,7 +14,7 @@ allow dom0_t xen_t:xen {
tmem_control getscheduler setscheduler
};
allow dom0_t xen_t:xen2 {
- resource_op psr_cmt_op psr_cat_op pmu_ctrl get_symbol
+ resource_op psr_cmt_op psr_alloc pmu_ctrl get_symbol
get_cpu_levelling_caps get_cpu_featureset livepatch_op
gcov_op
};
@@ -39,7 +39,7 @@ allow dom0_t dom0_t:domain {
};
allow dom0_t dom0_t:domain2 {
set_cpuid gettsc settsc setscheduler set_max_evtchn set_vnumainfo
- get_vnumainfo psr_cmt_op psr_cat_op
+ get_vnumainfo psr_cmt_op psr_alloc
};
allow dom0_t dom0_t:resource { add remove };
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 039b920..7e1c0d6 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -258,27 +258,27 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
switch ( type )
{
case XC_PSR_CAT_L3_CBM:
- cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM;
+ cmd = XEN_DOMCTL_PSR_ALLOC_SET_L3_CBM;
break;
case XC_PSR_CAT_L3_CBM_CODE:
- cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE;
+ cmd = XEN_DOMCTL_PSR_ALLOC_SET_L3_CODE;
break;
case XC_PSR_CAT_L3_CBM_DATA:
- cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA;
+ cmd = XEN_DOMCTL_PSR_ALLOC_SET_L3_DATA;
break;
case XC_PSR_CAT_L2_CBM:
- cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM;
+ cmd = XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM;
break;
default:
errno = EINVAL;
return -1;
}
- domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.cmd = XEN_DOMCTL_psr_alloc;
domctl.domain = (domid_t)domid;
- domctl.u.psr_cat_op.cmd = cmd;
- domctl.u.psr_cat_op.target = target;
- domctl.u.psr_cat_op.data = data;
+ domctl.u.psr_alloc.cmd = cmd;
+ domctl.u.psr_alloc.target = target;
+ domctl.u.psr_alloc.data = data;
return do_domctl(xch, &domctl);
}
@@ -294,31 +294,31 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
switch ( type )
{
case XC_PSR_CAT_L3_CBM:
- cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM;
+ cmd = XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM;
break;
case XC_PSR_CAT_L3_CBM_CODE:
- cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE;
+ cmd = XEN_DOMCTL_PSR_ALLOC_GET_L3_CODE;
break;
case XC_PSR_CAT_L3_CBM_DATA:
- cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA;
+ cmd = XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA;
break;
case XC_PSR_CAT_L2_CBM:
- cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM;
+ cmd = XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM;
break;
default:
errno = EINVAL;
return -1;
}
- domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.cmd = XEN_DOMCTL_psr_alloc;
domctl.domain = (domid_t)domid;
- domctl.u.psr_cat_op.cmd = cmd;
- domctl.u.psr_cat_op.target = target;
+ domctl.u.psr_alloc.cmd = cmd;
+ domctl.u.psr_alloc.target = target;
rc = do_domctl(xch, &domctl);
if ( !rc )
- *data = domctl.u.psr_cat_op.data;
+ *data = domctl.u.psr_alloc.data;
return rc;
}
@@ -329,30 +329,30 @@ int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
int rc = -1;
DECLARE_SYSCTL;
- sysctl.cmd = XEN_SYSCTL_psr_cat_op;
- sysctl.u.psr_cat_op.target = socket;
+ sysctl.cmd = XEN_SYSCTL_psr_alloc;
+ sysctl.u.psr_alloc.target = socket;
switch ( lvl )
{
case 2:
- sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
+ sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_l2_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_cat_op.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_cat_op.u.cat_info.cbm_len;
+ *cos_max = sysctl.u.psr_alloc.u.cat_info.cos_max;
+ *cbm_len = sysctl.u.psr_alloc.u.cat_info.cbm_len;
*cdp_enabled = false;
}
break;
case 3:
- sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
+ sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_l3_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_cat_op.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_cat_op.u.cat_info.cbm_len;
- *cdp_enabled = sysctl.u.psr_cat_op.u.cat_info.flags &
- XEN_SYSCTL_PSR_CAT_L3_CDP;
+ *cos_max = sysctl.u.psr_alloc.u.cat_info.cos_max;
+ *cbm_len = sysctl.u.psr_alloc.u.cat_info.cbm_len;
+ *cdp_enabled = sysctl.u.psr_alloc.u.cat_info.flags &
+ XEN_SYSCTL_PSR_ALLOC_L3_CDP;
}
break;
default:
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 127c84e..1424c90 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1439,60 +1439,60 @@ long arch_do_domctl(
}
break;
- case XEN_DOMCTL_psr_cat_op:
- switch ( domctl->u.psr_cat_op.cmd )
+ case XEN_DOMCTL_psr_alloc:
+ switch ( domctl->u.psr_alloc.cmd )
{
uint32_t val32;
- case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ case XEN_DOMCTL_PSR_ALLOC_SET_L3_CBM:
+ ret = psr_set_val(d, domctl->u.psr_alloc.target,
+ domctl->u.psr_alloc.data,
PSR_CBM_TYPE_L3);
break;
- case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ case XEN_DOMCTL_PSR_ALLOC_SET_L3_CODE:
+ ret = psr_set_val(d, domctl->u.psr_alloc.target,
+ domctl->u.psr_alloc.data,
PSR_CBM_TYPE_L3_CODE);
break;
- case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ case XEN_DOMCTL_PSR_ALLOC_SET_L3_DATA:
+ ret = psr_set_val(d, domctl->u.psr_alloc.target,
+ domctl->u.psr_alloc.data,
PSR_CBM_TYPE_L3_DATA);
break;
- case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ case XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM:
+ ret = psr_set_val(d, domctl->u.psr_alloc.target,
+ domctl->u.psr_alloc.data,
PSR_CBM_TYPE_L2);
break;
- case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ case XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM:
+ ret = psr_get_val(d, domctl->u.psr_alloc.target,
&val32, PSR_CBM_TYPE_L3);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc.data = val32;
copyback = true;
break;
- case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ case XEN_DOMCTL_PSR_ALLOC_GET_L3_CODE:
+ ret = psr_get_val(d, domctl->u.psr_alloc.target,
&val32, PSR_CBM_TYPE_L3_CODE);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc.data = val32;
copyback = true;
break;
- case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ case XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA:
+ ret = psr_get_val(d, domctl->u.psr_alloc.target,
&val32, PSR_CBM_TYPE_L3_DATA);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc.data = val32;
copyback = true;
break;
- case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ case XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM:
+ ret = psr_get_val(d, domctl->u.psr_alloc.target,
&val32, PSR_CBM_TYPE_L2);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc.data = val32;
copyback = true;
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index c2036cb..c0123d2 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -382,7 +382,7 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat,
if ( !cat_get_feat_info(feat, data, array_len) )
return false;
- data[PSR_INFO_IDX_CAT_FLAG] |= XEN_SYSCTL_PSR_CAT_L3_CDP;
+ data[PSR_INFO_IDX_CAT_FLAG] |= XEN_SYSCTL_PSR_ALLOC_L3_CDP;
return true;
}
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index c3fdae8..7dcbe74 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -171,45 +171,45 @@ long arch_do_sysctl(
break;
- case XEN_SYSCTL_psr_cat_op:
- switch ( sysctl->u.psr_cat_op.cmd )
+ case XEN_SYSCTL_psr_alloc:
+ switch ( sysctl->u.psr_alloc.cmd )
{
uint32_t data[PSR_INFO_ARRAY_SIZE];
- case XEN_SYSCTL_PSR_CAT_get_l3_info:
+ case XEN_SYSCTL_PSR_ALLOC_get_l3_info:
{
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc.target,
PSR_CBM_TYPE_L3, data, ARRAY_SIZE(data));
if ( ret )
break;
- sysctl->u.psr_cat_op.u.cat_info.cos_max =
+ sysctl->u.psr_alloc.u.cat_info.cos_max =
data[PSR_INFO_IDX_COS_MAX];
- sysctl->u.psr_cat_op.u.cat_info.cbm_len =
+ sysctl->u.psr_alloc.u.cat_info.cbm_len =
data[PSR_INFO_IDX_CAT_CBM_LEN];
- sysctl->u.psr_cat_op.u.cat_info.flags =
+ sysctl->u.psr_alloc.u.cat_info.flags =
data[PSR_INFO_IDX_CAT_FLAG];
- if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc) )
ret = -EFAULT;
break;
}
- case XEN_SYSCTL_PSR_CAT_get_l2_info:
+ case XEN_SYSCTL_PSR_ALLOC_get_l2_info:
{
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc.target,
PSR_CBM_TYPE_L2, data, ARRAY_SIZE(data));
if ( ret )
break;
- sysctl->u.psr_cat_op.u.cat_info.cos_max =
+ sysctl->u.psr_alloc.u.cat_info.cos_max =
data[PSR_INFO_IDX_COS_MAX];
- sysctl->u.psr_cat_op.u.cat_info.cbm_len =
+ sysctl->u.psr_alloc.u.cat_info.cbm_len =
data[PSR_INFO_IDX_CAT_CBM_LEN];
- sysctl->u.psr_cat_op.u.cat_info.flags =
+ sysctl->u.psr_alloc.u.cat_info.flags =
data[PSR_INFO_IDX_CAT_FLAG];
- if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc) )
ret = -EFAULT;
break;
}
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 0669c31..a953157 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -37,7 +37,7 @@
#include "hvm/save.h"
#include "memory.h"
-#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000e
+#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000f
/*
* NB. xen_domctl.domain is an IN/OUT parameter for this operation.
@@ -1135,21 +1135,21 @@ struct xen_domctl_monitor_op {
typedef struct xen_domctl_monitor_op xen_domctl_monitor_op_t;
DEFINE_XEN_GUEST_HANDLE(xen_domctl_monitor_op_t);
-struct xen_domctl_psr_cat_op {
-#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM 0
-#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM 1
-#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE 2
-#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA 3
-#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE 4
-#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
-#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
-#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
+struct xen_domctl_psr_alloc {
+#define XEN_DOMCTL_PSR_ALLOC_SET_L3_CBM 0
+#define XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM 1
+#define XEN_DOMCTL_PSR_ALLOC_SET_L3_CODE 2
+#define XEN_DOMCTL_PSR_ALLOC_SET_L3_DATA 3
+#define XEN_DOMCTL_PSR_ALLOC_GET_L3_CODE 4
+#define XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA 5
+#define XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM 6
+#define XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM 7
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target; /* IN */
uint64_t data; /* IN/OUT */
};
-typedef struct xen_domctl_psr_cat_op xen_domctl_psr_cat_op_t;
-DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_cat_op_t);
+typedef struct xen_domctl_psr_alloc xen_domctl_psr_alloc_t;
+DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_alloc_t);
struct xen_domctl {
uint32_t cmd;
@@ -1226,7 +1226,7 @@ struct xen_domctl {
#define XEN_DOMCTL_setvnumainfo 74
#define XEN_DOMCTL_psr_cmt_op 75
#define XEN_DOMCTL_monitor_op 77
-#define XEN_DOMCTL_psr_cat_op 78
+#define XEN_DOMCTL_psr_alloc 78
#define XEN_DOMCTL_soft_reset 79
#define XEN_DOMCTL_gdbsx_guestmemio 1000
#define XEN_DOMCTL_gdbsx_pausevcpu 1001
@@ -1289,7 +1289,7 @@ struct xen_domctl {
struct xen_domctl_vnuma vnuma;
struct xen_domctl_psr_cmt_op psr_cmt_op;
struct xen_domctl_monitor_op monitor_op;
- struct xen_domctl_psr_cat_op psr_cat_op;
+ struct xen_domctl_psr_alloc psr_alloc;
uint8_t pad[128];
} u;
};
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 9e51af6..4759b10 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -36,7 +36,7 @@
#include "physdev.h"
#include "tmem.h"
-#define XEN_SYSCTL_INTERFACE_VERSION 0x0000000F
+#define XEN_SYSCTL_INTERFACE_VERSION 0x00000010
/*
* Read console content from Xen buffer ring.
@@ -743,22 +743,22 @@ struct xen_sysctl_pcitopoinfo {
typedef struct xen_sysctl_pcitopoinfo xen_sysctl_pcitopoinfo_t;
DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
-#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
-#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
-struct xen_sysctl_psr_cat_op {
+#define XEN_SYSCTL_PSR_ALLOC_get_l3_info 0
+#define XEN_SYSCTL_PSR_ALLOC_get_l2_info 1
+struct xen_sysctl_psr_alloc {
uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
uint32_t target; /* IN */
union {
struct {
uint32_t cbm_len; /* OUT: CBM length */
uint32_t cos_max; /* OUT: Maximum COS */
-#define XEN_SYSCTL_PSR_CAT_L3_CDP (1u << 0)
+#define XEN_SYSCTL_PSR_ALLOC_L3_CDP (1u << 0)
uint32_t flags; /* OUT: CAT flags */
} cat_info;
} u;
};
-typedef struct xen_sysctl_psr_cat_op xen_sysctl_psr_cat_op_t;
-DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_cat_op_t);
+typedef struct xen_sysctl_psr_alloc xen_sysctl_psr_alloc_t;
+DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_alloc_t);
#define XEN_SYSCTL_TMEM_OP_ALL_CLIENTS 0xFFFFU
@@ -1119,7 +1119,7 @@ struct xen_sysctl {
#define XEN_SYSCTL_gcov_op 20
#define XEN_SYSCTL_psr_cmt_op 21
#define XEN_SYSCTL_pcitopoinfo 22
-#define XEN_SYSCTL_psr_cat_op 23
+#define XEN_SYSCTL_psr_alloc 23
#define XEN_SYSCTL_tmem_op 24
#define XEN_SYSCTL_get_cpu_levelling_caps 25
#define XEN_SYSCTL_get_cpu_featureset 26
@@ -1147,7 +1147,7 @@ struct xen_sysctl {
struct xen_sysctl_scheduler_op scheduler_op;
struct xen_sysctl_gcov_op gcov_op;
struct xen_sysctl_psr_cmt_op psr_cmt_op;
- struct xen_sysctl_psr_cat_op psr_cat_op;
+ struct xen_sysctl_psr_alloc psr_alloc;
struct xen_sysctl_tmem_op tmem_op;
struct xen_sysctl_cpu_levelling_caps cpu_levelling_caps;
struct xen_sysctl_cpu_featureset cpu_featureset;
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 9114627..69c9ffd 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -742,8 +742,8 @@ static int flask_domctl(struct domain *d, int cmd)
case XEN_DOMCTL_psr_cmt_op:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CMT_OP);
- case XEN_DOMCTL_psr_cat_op:
- return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CAT_OP);
+ case XEN_DOMCTL_psr_alloc_op:
+ return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_ALLOC_OP);
case XEN_DOMCTL_soft_reset:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
@@ -806,9 +806,9 @@ static int flask_sysctl(int cmd)
case XEN_SYSCTL_psr_cmt_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
XEN2__PSR_CMT_OP, NULL);
- case XEN_SYSCTL_psr_cat_op:
+ case XEN_SYSCTL_psr_alloc_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
- XEN2__PSR_CAT_OP, NULL);
+ XEN2__PSR_ALLOC_OP, NULL);
case XEN_SYSCTL_tmem_op:
return domain_has_xen(current->domain, XEN__TMEM_CONTROL);
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 1f7eb35..9d81e41 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -85,8 +85,8 @@ class xen2
resource_op
# XEN_SYSCTL_psr_cmt_op
psr_cmt_op
-# XEN_SYSCTL_psr_cat_op
- psr_cat_op
+# XEN_SYSCTL_psr_alloc_op
+ psr_alloc_op
# XENPF_get_symbol
get_symbol
# PMU control
@@ -244,8 +244,8 @@ class domain2
mem_paging
# XENMEM_sharing_op
mem_sharing
-# XEN_DOMCTL_psr_cat_op
- psr_cat_op
+# XEN_DOMCTL_psr_alloc_op
+ psr_alloc_op
}
# Similar to class domain, but primarily contains domctls related to HVM domains
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-09-05 9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-09-05 9:32 ` [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 8:22 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA Yi Sun
` (11 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch renames 'cbm_type' to 'psr_type' to make it be general.
Then, we can reuse this for all psr allocation features.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
---
v3:
- replace 'psr_val_type' to 'psr_type' and remove '_VAL' from the enum
items.
(suggested by Roger Pau Monné)
v2:
- replace 'PSR_VAL_TYPE_{L3, L2}' to 'PSR_VAL_TYPE_{L3, L2}_CBM'.
(suggested by Chao Peng)
---
xen/arch/x86/domctl.c | 16 ++++++------
xen/arch/x86/psr.c | 62 +++++++++++++++++++++++++----------------------
xen/arch/x86/sysctl.c | 4 +--
xen/include/asm-x86/psr.h | 18 +++++++-------
4 files changed, 52 insertions(+), 48 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 1424c90..696eff2 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1447,51 +1447,51 @@ long arch_do_domctl(
case XEN_DOMCTL_PSR_ALLOC_SET_L3_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc.target,
domctl->u.psr_alloc.data,
- PSR_CBM_TYPE_L3);
+ PSR_TYPE_L3_CBM);
break;
case XEN_DOMCTL_PSR_ALLOC_SET_L3_CODE:
ret = psr_set_val(d, domctl->u.psr_alloc.target,
domctl->u.psr_alloc.data,
- PSR_CBM_TYPE_L3_CODE);
+ PSR_TYPE_L3_CODE);
break;
case XEN_DOMCTL_PSR_ALLOC_SET_L3_DATA:
ret = psr_set_val(d, domctl->u.psr_alloc.target,
domctl->u.psr_alloc.data,
- PSR_CBM_TYPE_L3_DATA);
+ PSR_TYPE_L3_DATA);
break;
case XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc.target,
domctl->u.psr_alloc.data,
- PSR_CBM_TYPE_L2);
+ PSR_TYPE_L2_CBM);
break;
case XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc.target,
- &val32, PSR_CBM_TYPE_L3);
+ &val32, PSR_TYPE_L3_CBM);
domctl->u.psr_alloc.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_ALLOC_GET_L3_CODE:
ret = psr_get_val(d, domctl->u.psr_alloc.target,
- &val32, PSR_CBM_TYPE_L3_CODE);
+ &val32, PSR_TYPE_L3_CODE);
domctl->u.psr_alloc.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA:
ret = psr_get_val(d, domctl->u.psr_alloc.target,
- &val32, PSR_CBM_TYPE_L3_DATA);
+ &val32, PSR_TYPE_L3_DATA);
domctl->u.psr_alloc.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc.target,
- &val32, PSR_CBM_TYPE_L2);
+ &val32, PSR_TYPE_L2_CBM);
domctl->u.psr_alloc.data = val32;
copyback = true;
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index c0123d2..4166a1c 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -100,24 +100,24 @@ static const struct feat_props {
unsigned int cos_num;
/*
- * An array to save all 'enum cbm_type' values of the feature. It is
+ * An array to save all 'enum psr_type' values of the feature. It is
* used with cos_num together to get/write a feature's COS registers
* values one by one.
*/
- enum cbm_type type[MAX_COS_NUM];
+ enum psr_type type[MAX_COS_NUM];
/*
* alt_type is 'alternative type'. When this 'alt_type' is input, the
* feature does some special operations.
*/
- enum cbm_type alt_type;
+ enum psr_type alt_type;
/* get_feat_info is used to return feature HW info through sysctl. */
bool (*get_feat_info)(const struct feat_node *feat,
uint32_t data[], unsigned int array_len);
/* write_msr is used to write out feature MSR register. */
- void (*write_msr)(unsigned int cos, uint32_t val, enum cbm_type type);
+ void (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type);
} *feat_props[FEAT_TYPE_NUM];
/*
@@ -215,13 +215,13 @@ static void free_socket_resources(unsigned int socket)
bitmap_zero(info->dom_set, DOMID_IDLE + 1);
}
-static enum psr_feat_type psr_cbm_type_to_feat_type(enum cbm_type type)
+static enum psr_feat_type psr_type_to_feat_type(enum psr_type type)
{
enum psr_feat_type feat_type = FEAT_TYPE_UNKNOWN;
switch ( type )
{
- case PSR_CBM_TYPE_L3:
+ case PSR_TYPE_L3_CBM:
feat_type = FEAT_TYPE_L3_CAT;
/*
@@ -233,12 +233,12 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum cbm_type type)
break;
- case PSR_CBM_TYPE_L3_DATA:
- case PSR_CBM_TYPE_L3_CODE:
+ case PSR_TYPE_L3_DATA:
+ case PSR_TYPE_L3_CODE:
feat_type = FEAT_TYPE_L3_CDP;
break;
- case PSR_CBM_TYPE_L2:
+ case PSR_TYPE_L2_CBM:
feat_type = FEAT_TYPE_L2_CAT;
break;
@@ -362,15 +362,16 @@ static bool cat_get_feat_info(const struct feat_node *feat,
}
/* L3 CAT props */
-static void l3_cat_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
+static void l3_cat_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val);
}
static const struct feat_props l3_cat_props = {
.cos_num = 1,
- .type[0] = PSR_CBM_TYPE_L3,
- .alt_type = PSR_CBM_TYPE_UNKNOWN,
+ .type[0] = PSR_TYPE_L3_CBM,
+ .alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l3_cat_write_msr,
};
@@ -387,9 +388,10 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat,
return true;
}
-static void l3_cdp_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
+static void l3_cdp_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
- wrmsrl(((type == PSR_CBM_TYPE_L3_DATA) ?
+ wrmsrl(((type == PSR_TYPE_L3_DATA) ?
MSR_IA32_PSR_L3_MASK_DATA(cos) :
MSR_IA32_PSR_L3_MASK_CODE(cos)),
val);
@@ -397,23 +399,24 @@ static void l3_cdp_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
static const struct feat_props l3_cdp_props = {
.cos_num = 2,
- .type[0] = PSR_CBM_TYPE_L3_DATA,
- .type[1] = PSR_CBM_TYPE_L3_CODE,
- .alt_type = PSR_CBM_TYPE_L3,
+ .type[0] = PSR_TYPE_L3_DATA,
+ .type[1] = PSR_TYPE_L3_CODE,
+ .alt_type = PSR_TYPE_L3_CBM,
.get_feat_info = l3_cdp_get_feat_info,
.write_msr = l3_cdp_write_msr,
};
/* L2 CAT props */
-static void l2_cat_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
+static void l2_cat_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val);
}
static const struct feat_props l2_cat_props = {
.cos_num = 1,
- .type[0] = PSR_CBM_TYPE_L2,
- .alt_type = PSR_CBM_TYPE_UNKNOWN,
+ .type[0] = PSR_TYPE_L2_CBM,
+ .alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l2_cat_write_msr,
};
@@ -654,7 +657,7 @@ static struct psr_socket_info *get_socket_info(unsigned int socket)
return socket_info + socket;
}
-int psr_get_info(unsigned int socket, enum cbm_type type,
+int psr_get_info(unsigned int socket, enum psr_type type,
uint32_t data[], unsigned int array_len)
{
const struct psr_socket_info *info = get_socket_info(socket);
@@ -666,7 +669,7 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
if ( IS_ERR(info) )
return PTR_ERR(info);
- feat_type = psr_cbm_type_to_feat_type(type);
+ feat_type = psr_type_to_feat_type(type);
if ( feat_type >= ARRAY_SIZE(info->features) )
return -ENOENT;
@@ -687,7 +690,7 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
}
int psr_get_val(struct domain *d, unsigned int socket,
- uint32_t *val, enum cbm_type type)
+ uint32_t *val, enum psr_type type)
{
const struct psr_socket_info *info = get_socket_info(socket);
const struct feat_node *feat;
@@ -699,7 +702,7 @@ int psr_get_val(struct domain *d, unsigned int socket,
if ( IS_ERR(info) )
return PTR_ERR(info);
- feat_type = psr_cbm_type_to_feat_type(type);
+ feat_type = psr_type_to_feat_type(type);
if ( feat_type >= ARRAY_SIZE(info->features) )
return -ENOENT;
@@ -829,7 +832,7 @@ static int insert_val_into_array(uint32_t val[],
unsigned int array_len,
const struct psr_socket_info *info,
enum psr_feat_type feat_type,
- enum cbm_type type,
+ enum psr_type type,
uint32_t new_val)
{
const struct feat_node *feat;
@@ -865,8 +868,9 @@ static int insert_val_into_array(uint32_t val[],
/*
* Value setting position is same as feature array.
* For CDP, user may set both DATA and CODE to same value. For such case,
- * user input 'PSR_CBM_TYPE_L3' as type. The alternative type of CDP is same
- * as it. So we should set new_val to both of DATA and CODE under such case.
+ * user input 'PSR_TYPE_L3_CBM' as type. The alternative type of CDP is
+ * same as it. So we should set new_val to both of DATA and CODE under such
+ * case.
*/
for ( i = 0; i < props->cos_num; i++ )
{
@@ -1155,7 +1159,7 @@ static int write_psr_msrs(unsigned int socket, unsigned int cos,
}
int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t new_val, enum cbm_type type)
+ uint64_t new_val, enum psr_type type)
{
unsigned int old_cos, array_len;
int cos, ret;
@@ -1171,7 +1175,7 @@ int psr_set_val(struct domain *d, unsigned int socket,
if ( new_val != val )
return -EINVAL;
- feat_type = psr_cbm_type_to_feat_type(type);
+ feat_type = psr_type_to_feat_type(type);
if ( feat_type >= ARRAY_SIZE(info->features) ||
!info->features[feat_type] )
return -ENOENT;
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 7dcbe74..1d3dbd0 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -179,7 +179,7 @@ long arch_do_sysctl(
case XEN_SYSCTL_PSR_ALLOC_get_l3_info:
{
ret = psr_get_info(sysctl->u.psr_alloc.target,
- PSR_CBM_TYPE_L3, data, ARRAY_SIZE(data));
+ PSR_TYPE_L3_CBM, data, ARRAY_SIZE(data));
if ( ret )
break;
@@ -198,7 +198,7 @@ long arch_do_sysctl(
case XEN_SYSCTL_PSR_ALLOC_get_l2_info:
{
ret = psr_get_info(sysctl->u.psr_alloc.target,
- PSR_CBM_TYPE_L2, data, ARRAY_SIZE(data));
+ PSR_TYPE_L2_CBM, data, ARRAY_SIZE(data));
if ( ret )
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 18a42f3..cb3f067 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -53,12 +53,12 @@ struct psr_cmt {
struct psr_cmt_l3 l3;
};
-enum cbm_type {
- PSR_CBM_TYPE_L3,
- PSR_CBM_TYPE_L3_CODE,
- PSR_CBM_TYPE_L3_DATA,
- PSR_CBM_TYPE_L2,
- PSR_CBM_TYPE_UNKNOWN,
+enum psr_type {
+ PSR_TYPE_L3_CBM,
+ PSR_TYPE_L3_CODE,
+ PSR_TYPE_L3_DATA,
+ PSR_TYPE_L2_CBM,
+ PSR_TYPE_UNKNOWN,
};
extern struct psr_cmt *psr_cmt;
@@ -72,12 +72,12 @@ int psr_alloc_rmid(struct domain *d);
void psr_free_rmid(struct domain *d);
void psr_ctxt_switch_to(struct domain *d);
-int psr_get_info(unsigned int socket, enum cbm_type type,
+int psr_get_info(unsigned int socket, enum psr_type type,
uint32_t data[], unsigned int array_len);
int psr_get_val(struct domain *d, unsigned int socket,
- uint32_t *val, enum cbm_type type);
+ uint32_t *val, enum psr_type type);
int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t val, enum cbm_type type);
+ uint64_t val, enum psr_type type);
void psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
--
1.9.1
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (2 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 8:55 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 05/15] x86: implement get hw info " Yi Sun
` (10 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements main data structures of MBA.
Like CAT features, MBA HW info has cos_max which means the max thrtl
register number, and thrtl_max which means the max throttle value
(delay value). It also has a flag to represent if the throttle
value is linear or not.
One thrtl register of MBA stores a throttle value for one or more
domains. The throttle value means the transaction time between L2
cache and next level memory to be delayed.
This patch also implements init flow for MBA and register stub
callback functions.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- replace 'psr_val_type' to 'psr_type'. Also, change 'PSR_VAL_TYPE_MBA' to
'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
- replace 'MBA_LINEAR' to 'MBA_LINEAR_MASK' to make the name more clear.
(suggested by Roger Pau Monné)
- replase 'cat_info'/'mba_info' to 'cat'/'mba' to make the names shorter.
(suggested by Roger Pau Monné)
- change type of 'linear' to 'bool'.
(suggested by Roger Pau Monné)
- make format string of printf in one line.
(suggested by Roger Pau Monné)
v2:
- modify commit message to replace 'cos register' to 'thrtl register' to
make it accurate.
(suggested by Chao Peng)
- restore the place of the sentence to assign value to 'feat->cbm_len'
because the MBA init flow is splitted out as a separate function in v1.
(suggested by Chao Peng)
- add comment to explain what the MBA thrtl defaul value '0' stands for.
(suggested by Chao Peng)
- check 'thrtl_max' under linear mode. It could not be euqal or larger than
100.
(suggested by Chao Peng)
v1:
- rebase codes onto L2 CAT v15.
- move comment to appropriate place.
(suggested by Chao Peng)
- implement 'mba_init_feature' and keep 'cat_init_feature'.
(suggested by Chao Peng)
- keep 'regs.b' into a local variable to avoid reading CPUID every time.
(suggested by Chao Peng)
---
xen/arch/x86/psr.c | 140 ++++++++++++++++++++++++++++++++++------
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 2 +
3 files changed, 125 insertions(+), 18 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 4166a1c..10776d2 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -27,13 +27,16 @@
* - CMT Cache Monitoring Technology
* - COS/CLOS Class of Service. Also mean COS registers.
* - COS_MAX Max number of COS for the feature (minus 1)
+ * - MBA Memory Bandwidth Allocation
* - MSRs Machine Specific Registers
* - PSR Intel Platform Shared Resource
+ * - THRTL_MAX Max throttle value (delay value) of MBA
*/
#define PSR_CMT (1u << 0)
#define PSR_CAT (1u << 1)
#define PSR_CDP (1u << 2)
+#define PSR_MBA (1u << 3)
#define CAT_CBM_LEN_MASK 0x1f
#define CAT_COS_MAX_MASK 0xffff
@@ -60,10 +63,14 @@
*/
#define MAX_COS_NUM 2
+#define MBA_LINEAR_MASK (1u << 2)
+#define MBA_THRTL_MAX_MASK 0xfff
+
enum psr_feat_type {
FEAT_TYPE_L3_CAT,
FEAT_TYPE_L3_CDP,
FEAT_TYPE_L2_CAT,
+ FEAT_TYPE_MBA,
FEAT_TYPE_NUM,
FEAT_TYPE_UNKNOWN,
};
@@ -71,7 +78,6 @@ enum psr_feat_type {
/*
* This structure represents one feature.
* cos_max - The max COS registers number got through CPUID.
- * cbm_len - The length of CBM got through CPUID.
* cos_reg_val - Array to store the values of COS registers. One entry stores
* the value of one COS register.
* For L3 CAT and L2 CAT, one entry corresponds to one COS_ID.
@@ -80,9 +86,23 @@ enum psr_feat_type {
* cos_reg_val[1] (Code).
*/
struct feat_node {
- /* cos_max and cbm_len are common values for all features so far. */
+ /* cos_max is common values for all features so far. */
unsigned int cos_max;
- unsigned int cbm_len;
+
+ /* Feature specific HW info. */
+ union {
+ struct {
+ /* The length of CBM got through CPUID. */
+ unsigned int cbm_len;
+ } cat;
+
+ struct {
+ /* The max throttling value got through CPUID. */
+ unsigned int thrtl_max;
+ bool linear;
+ } mba;
+ };
+
uint32_t cos_reg_val[MAX_COS_REG_CNT];
};
@@ -161,6 +181,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
*/
static struct feat_node *feat_l3;
static struct feat_node *feat_l2_cat;
+static struct feat_node *feat_mba;
/* Common functions */
#define cat_default_val(len) (0xffffffff >> (32 - (len)))
@@ -272,7 +293,7 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
return true;
}
-/* CAT common functions implementation. */
+/* Implementation of allocation features' functions. */
static int cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
struct psr_socket_info *info,
@@ -288,8 +309,8 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
if ( !regs->a || !regs->d )
return -ENOENT;
- feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
+ feat->cat.cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
switch ( type )
{
@@ -299,12 +320,12 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
return -ENOENT;
/* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
- feat->cos_reg_val[0] = cat_default_val(feat->cbm_len);
+ feat->cos_reg_val[0] = cat_default_val(feat->cat.cbm_len);
wrmsrl((type == FEAT_TYPE_L3_CAT ?
MSR_IA32_PSR_L3_MASK(0) :
MSR_IA32_PSR_L2_MASK(0)),
- cat_default_val(feat->cbm_len));
+ cat_default_val(feat->cat.cbm_len));
break;
@@ -319,11 +340,13 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
feat->cos_max = (feat->cos_max - 1) >> 1;
/* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
- get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len);
- get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len);
+ get_cdp_code(feat, 0) = cat_default_val(feat->cat.cbm_len);
+ get_cdp_data(feat, 0) = cat_default_val(feat->cat.cbm_len);
- wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len));
- wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len));
+ wrmsrl(MSR_IA32_PSR_L3_MASK(0),
+ cat_default_val(feat->cat.cbm_len));
+ wrmsrl(MSR_IA32_PSR_L3_MASK(1),
+ cat_default_val(feat->cat.cbm_len));
rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
wrmsrl(MSR_IA32_PSR_L3_QOS_CFG,
val | (1ull << PSR_L3_QOS_CDP_ENABLE_BIT));
@@ -343,7 +366,50 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
cat_feat_name[type], cpu_to_socket(smp_processor_id()),
- feat->cos_max, feat->cbm_len);
+ feat->cos_max, feat->cat.cbm_len);
+
+ return 0;
+}
+
+static int mba_init_feature(const struct cpuid_leaf *regs,
+ struct feat_node *feat,
+ struct psr_socket_info *info,
+ enum psr_feat_type type)
+{
+ /* No valid value so do not enable feature. */
+ if ( !regs->a || !regs->d )
+ return -ENOENT;
+
+ if ( type != FEAT_TYPE_MBA )
+ return -ENOENT;
+
+ feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
+ if ( feat->cos_max < 1 )
+ return -ENOENT;
+
+ feat->mba.thrtl_max = (regs->a & MBA_THRTL_MAX_MASK) + 1;
+
+ if ( regs->c & MBA_LINEAR_MASK )
+ {
+ feat->mba.linear = true;
+
+ if ( feat->mba.thrtl_max >= 100 )
+ return -ENOENT;
+ }
+
+ /* We reserve cos=0 as default thrtl (0) which means no delay. */
+ feat->cos_reg_val[0] = 0;
+ wrmsrl(MSR_IA32_PSR_MBA_MASK(0), 0);
+
+ /* Add this feature into array. */
+ info->features[type] = feat;
+
+ if ( !opt_cpu_info )
+ return 0;
+
+ printk(XENLOG_INFO "MBA: enabled on socket %u, cos_max:%u, thrtl_max:%u, linear:%u.\n",
+ cpu_to_socket(smp_processor_id()),
+ feat->cos_max, feat->mba.thrtl_max, feat->mba.linear);
return 0;
}
@@ -355,7 +421,7 @@ static bool cat_get_feat_info(const struct feat_node *feat,
return false;
data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
- data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cbm_len;
+ data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cat.cbm_len;
data[PSR_INFO_IDX_CAT_FLAG] = 0;
return true;
@@ -421,6 +487,26 @@ static const struct feat_props l2_cat_props = {
.write_msr = l2_cat_write_msr,
};
+/* MBA props */
+static bool mba_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], unsigned int array_len)
+{
+ return false;
+}
+
+static void mba_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
+{
+}
+
+static const struct feat_props mba_props = {
+ .cos_num = 1,
+ .type[0] = PSR_TYPE_MBA_THRTL,
+ .alt_type = PSR_TYPE_UNKNOWN,
+ .get_feat_info = mba_get_feat_info,
+ .write_msr = mba_write_msr,
+};
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -456,6 +542,7 @@ static void __init parse_psr_param(char *s)
parse_psr_bool(s, val_str, "cmt", PSR_CMT);
parse_psr_bool(s, val_str, "cat", PSR_CAT);
parse_psr_bool(s, val_str, "cdp", PSR_CDP);
+ parse_psr_bool(s, val_str, "mba", PSR_MBA);
if ( val_str && !strcmp(s, "rmid_max") )
opt_rmid_max = simple_strtoul(val_str, NULL, 0);
@@ -862,7 +949,7 @@ static int insert_val_into_array(uint32_t val[],
if ( array_len < props->cos_num )
return -ENOSPC;
- if ( !psr_check_cbm(feat->cbm_len, new_val) )
+ if ( !psr_check_cbm(feat->cat.cbm_len, new_val) )
return -EINVAL;
/*
@@ -1380,6 +1467,10 @@ static int psr_cpu_prepare(void)
(feat_l2_cat = xzalloc(struct feat_node)) == NULL )
return -ENOMEM;
+ if ( feat_mba == NULL &&
+ (feat_mba = xzalloc(struct feat_node)) == NULL )
+ return -ENOMEM;
+
return 0;
}
@@ -1389,6 +1480,7 @@ static void psr_cpu_init(void)
unsigned int socket, cpu = smp_processor_id();
struct feat_node *feat;
struct cpuid_leaf regs;
+ uint32_t reg_b;
if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) )
goto assoc_init;
@@ -1407,7 +1499,8 @@ static void psr_cpu_init(void)
spin_lock_init(&info->ref_lock);
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
- if ( regs.b & PSR_RESOURCE_TYPE_L3 )
+ reg_b = regs.b;
+ if ( reg_b & PSR_RESOURCE_TYPE_L3 )
{
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s);
@@ -1428,8 +1521,7 @@ static void psr_cpu_init(void)
}
}
- cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
- if ( regs.b & PSR_RESOURCE_TYPE_L2 )
+ if ( reg_b & PSR_RESOURCE_TYPE_L2 )
{
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);
@@ -1441,6 +1533,18 @@ static void psr_cpu_init(void)
feat_l2_cat = feat;
}
+ if ( reg_b & PSR_RESOURCE_TYPE_MBA )
+ {
+ cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, ®s);
+
+ feat = feat_mba;
+ feat_mba = NULL;
+ if ( !mba_init_feature(®s, feat, info, FEAT_TYPE_MBA) )
+ feat_props[FEAT_TYPE_MBA] = &mba_props;
+ else
+ feat_mba = feat;
+ }
+
info->feat_init = true;
assoc_init:
@@ -1500,7 +1604,7 @@ static int __init psr_presmp_init(void)
if ( (opt_psr & PSR_CMT) && opt_rmid_max )
init_psr_cmt(opt_rmid_max);
- if ( opt_psr & (PSR_CAT | PSR_CDP) )
+ if ( opt_psr & (PSR_CAT | PSR_CDP | PSR_MBA) )
init_psr();
if ( psr_cpu_prepare() )
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 4e08de6..41f1677 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -348,6 +348,7 @@
#define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1)
#define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2)
#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n))
+#define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x000000c1 + (n))
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index cb3f067..9d14264 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -24,6 +24,7 @@
/* Resource Type Enumeration */
#define PSR_RESOURCE_TYPE_L3 0x2
#define PSR_RESOURCE_TYPE_L2 0x4
+#define PSR_RESOURCE_TYPE_MBA 0x8
/* L3 Monitoring Features */
#define PSR_CMT_L3_OCCUPANCY 0x1
@@ -58,6 +59,7 @@ enum psr_type {
PSR_TYPE_L3_CODE,
PSR_TYPE_L3_DATA,
PSR_TYPE_L2_CBM,
+ PSR_TYPE_MBA_THRTL,
PSR_TYPE_UNKNOWN,
};
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 05/15] x86: implement get hw info flow for MBA
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (3 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 9:08 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 06/15] x86: implement get value interface " Yi Sun
` (9 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements get HW info flow for MBA including its callback
function and sysctl interface.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- replace 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
v2:
- use 'XEN_SYSCTL_PSR_MBA_LINEAR' to set MBA feature HW info.
(suggested by Chao Peng)
v1:
- sort 'PSR_INFO_IDX_' macros as feature.
(suggested by Chao Peng)
- rename 'PSR_INFO_IDX_MBA_LINEAR' to 'PSR_INFO_IDX_MBA_FLAG'.
- rename 'linear' in 'struct mba_info' to 'flags' for future extension.
(suggested by Chao Peng)
---
xen/arch/x86/psr.c | 17 ++++++++++++++++-
xen/arch/x86/sysctl.c | 19 +++++++++++++++++++
xen/include/asm-x86/psr.h | 2 ++
xen/include/public/sysctl.h | 8 ++++++++
4 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 10776d2..0486d2d 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -263,6 +263,10 @@ static enum psr_feat_type psr_type_to_feat_type(enum psr_type type)
feat_type = FEAT_TYPE_L2_CAT;
break;
+ case PSR_TYPE_MBA_THRTL:
+ feat_type = FEAT_TYPE_MBA;
+ break;
+
default:
ASSERT_UNREACHABLE();
}
@@ -491,7 +495,18 @@ static const struct feat_props l2_cat_props = {
static bool mba_get_feat_info(const struct feat_node *feat,
uint32_t data[], unsigned int array_len)
{
- return false;
+ if ( array_len != PSR_INFO_ARRAY_SIZE )
+ return false;
+
+ data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
+ data[PSR_INFO_IDX_MBA_THRTL_MAX] = feat->mba.thrtl_max;
+
+ if ( feat->mba.linear )
+ data[PSR_INFO_IDX_MBA_FLAG] |= XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
+ else
+ data[PSR_INFO_IDX_MBA_FLAG] &= ~XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
+
+ return true;
}
static void mba_write_msr(unsigned int cos, uint32_t val,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 1d3dbd0..4634cad 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -214,6 +214,25 @@ long arch_do_sysctl(
break;
}
+ case XEN_SYSCTL_PSR_ALLOC_get_mba_info:
+ {
+ ret = psr_get_info(sysctl->u.psr_alloc.target,
+ PSR_TYPE_MBA_THRTL, data, ARRAY_SIZE(data));
+ if ( ret )
+ break;
+
+ sysctl->u.psr_alloc.u.mba_info.cos_max =
+ data[PSR_INFO_IDX_COS_MAX];
+ sysctl->u.psr_alloc.u.mba_info.thrtl_max =
+ data[PSR_INFO_IDX_MBA_THRTL_MAX];
+ sysctl->u.psr_alloc.u.mba_info.flags =
+ data[PSR_INFO_IDX_MBA_FLAG];
+
+ if ( __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc) )
+ ret = -EFAULT;
+ break;
+ }
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 9d14264..084ae97 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -39,6 +39,8 @@
#define PSR_INFO_IDX_COS_MAX 0
#define PSR_INFO_IDX_CAT_CBM_LEN 1
#define PSR_INFO_IDX_CAT_FLAG 2
+#define PSR_INFO_IDX_MBA_THRTL_MAX 1
+#define PSR_INFO_IDX_MBA_FLAG 2
#define PSR_INFO_ARRAY_SIZE 3
struct psr_cmt_l3 {
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 4759b10..0cfe02d 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -745,6 +745,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
#define XEN_SYSCTL_PSR_ALLOC_get_l3_info 0
#define XEN_SYSCTL_PSR_ALLOC_get_l2_info 1
+#define XEN_SYSCTL_PSR_ALLOC_get_mba_info 2
struct xen_sysctl_psr_alloc {
uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
uint32_t target; /* IN */
@@ -755,6 +756,13 @@ struct xen_sysctl_psr_alloc {
#define XEN_SYSCTL_PSR_ALLOC_L3_CDP (1u << 0)
uint32_t flags; /* OUT: CAT flags */
} cat_info;
+
+ struct {
+ uint32_t thrtl_max; /* OUT: Maximum throttle */
+ uint32_t cos_max; /* OUT: Maximum COS */
+#define XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR (1u << 0)
+ uint32_t flags; /* OUT: MBA flags */
+ } mba_info;
} u;
};
typedef struct xen_sysctl_psr_alloc xen_sysctl_psr_alloc_t;
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 06/15] x86: implement get value interface for MBA
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (4 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 05/15] x86: implement get hw info " Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 9:15 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 07/15] x86: implement set value flow " Yi Sun
` (8 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements get value domctl interface for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
---
v3:
- change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
---
xen/arch/x86/domctl.c | 7 +++++++
xen/include/public/domctl.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 696eff2..7902af7 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1496,6 +1496,13 @@ long arch_do_domctl(
copyback = true;
break;
+ case XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL:
+ ret = psr_get_val(d, domctl->u.psr_alloc.target,
+ &val32, PSR_TYPE_MBA_THRTL);
+ domctl->u.psr_alloc.data = val32;
+ copyback = true;
+ break;
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index a953157..8be38cc 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc {
#define XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target; /* IN */
uint64_t data; /* IN/OUT */
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 07/15] x86: implement set value flow for MBA
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (5 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 06/15] x86: implement get value interface " Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 9:57 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 08/15] tools: create general interfaces to support psr allocation features Yi Sun
` (7 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements set value flow for MBA including its callback
function and domctl interface.
It also changes the memebers in 'cos_write_info' to transfer the
feature array, feature properties array and value array. Then, we
can write all features values on the cos id into MSRs.
Because multiple features may co-exist, we need handle all features to write
values of them into a COS register with new COS ID. E.g:
1. L3 CAT and MBA co-exist.
2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of Dom1 is 0x1ff,
the MBA Thrtle of Dom1 is 0xa.
3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because COS ID 2 is
used by Dom2 too, we have to pick a new COS ID 3. The values of Dom1 on
COS ID 3 are all default values as below:
---------
| COS 3 |
---------
L3 CAT | 0x7ff |
---------
MBA | 0x0 |
---------
4. After setting, the L3 CAT CBM value of Dom1 should be kept and the new MBA
Thrtl is set. So, the values on COS ID 3 should be below.
---------
| COS 3 |
---------
L3 CAT | 0x1ff |
---------
MBA | 0x14 |
---------
So, we should write all features values into their MSRs. That requires the
feature array, feature properties array and value array are input.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- modify commit message to make it clear.
(suggested by Roger Pau Monné)
- modify functionality of 'check_val' to make it simple to only check value.
Change the last parameter type from 'unsigned long *' to 'unsigned long'.
(suggested by Roger Pau Monné)
- call rdmsrl to get value just written into MSR for MBA. Because HW can
automatically change input value to what it wants.
(suggested by Roger Pau Monné)
- change type of 'write_msr' to 'uint32_t' to return the value actually
written into MSR. Then, change 'do_write_psr_msrs' to set the returned
value into 'cos_reg_val[]'
- move the declaration of 'j' into loop in 'do_write_psr_msrs'.
(suggested by Roger Pau Monné)
- change 'mba_info' to 'mba'.
(suggested by Roger Pau Monné)
- change 'cat_info' to 'cat'.
(suggested by Roger Pau Monné)
- rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
from name.
(suggested by Roger Pau Monné)
- change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
v2:
- remove linear mode 'thrtl_max' check in 'mba_check_thrtl' because it has
been checked in 'mba_init_feature'.
(suggested by Chao Peng)
- for non-linear mode, check if '*thrtl' is not 0 in 'mba_check_thrtl'. If
it is 0, we do not need to change it.
(suggested by Chao Peng)
- move comments to explain changes of 'cos_write_info' from psr.c to commit
message.
(suggested by Chao Peng)
---
xen/arch/x86/domctl.c | 6 ++
xen/arch/x86/psr.c | 146 +++++++++++++++++++++++++++-----------------
xen/include/public/domctl.h | 1 +
3 files changed, 96 insertions(+), 57 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 7902af7..8550d06 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1468,6 +1468,12 @@ long arch_do_domctl(
PSR_TYPE_L2_CBM);
break;
+ case XEN_DOMCTL_PSR_ALLOC_SET_MBA_THRTL:
+ ret = psr_set_val(d, domctl->u.psr_alloc.target,
+ domctl->u.psr_alloc.data,
+ PSR_TYPE_MBA_THRTL);
+ break;
+
case XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc.target,
&val32, PSR_TYPE_L3_CBM);
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 0486d2d..d633194 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -137,7 +137,10 @@ static const struct feat_props {
uint32_t data[], unsigned int array_len);
/* write_msr is used to write out feature MSR register. */
- void (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type);
+ uint32_t (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type);
+
+ /* check_val is used to check if input val fulfills SDM requirement. */
+ bool (*check_val)(const struct feat_node *feat, unsigned long val);
} *feat_props[FEAT_TYPE_NUM];
/*
@@ -274,29 +277,6 @@ static enum psr_feat_type psr_type_to_feat_type(enum psr_type type)
return feat_type;
}
-static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
-{
- unsigned int first_bit, zero_bit;
-
- /* Set bits should only in the range of [0, cbm_len]. */
- if ( cbm & (~0ul << cbm_len) )
- return false;
-
- /* At least one bit need to be set. */
- if ( cbm == 0 )
- return false;
-
- first_bit = find_first_bit(&cbm, cbm_len);
- zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
-
- /* Set bits should be contiguous. */
- if ( zero_bit < cbm_len &&
- find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
- return false;
-
- return true;
-}
-
/* Implementation of allocation features' functions. */
static int cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
@@ -431,11 +411,37 @@ static bool cat_get_feat_info(const struct feat_node *feat,
return true;
}
+static bool cat_check_cbm(const struct feat_node *feat, unsigned long cbm)
+{
+ unsigned int first_bit, zero_bit;
+ unsigned int cbm_len = feat->cat.cbm_len;
+
+ /* Set bits should only in the range of [0, cbm_len]. */
+ if ( cbm & (~0ul << cbm_len) )
+ return false;
+
+ /* At least one bit need to be set. */
+ if ( cbm == 0 )
+ return false;
+
+ first_bit = find_first_bit(&cbm, cbm_len);
+ zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
+
+ /* Set bits should be contiguous. */
+ if ( zero_bit < cbm_len &&
+ find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
+ return false;
+
+ return true;
+}
+
/* L3 CAT props */
-static void l3_cat_write_msr(unsigned int cos, uint32_t val,
- enum psr_type type)
+static uint32_t l3_cat_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val);
+
+ return val;
}
static const struct feat_props l3_cat_props = {
@@ -444,6 +450,7 @@ static const struct feat_props l3_cat_props = {
.alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l3_cat_write_msr,
+ .check_val = cat_check_cbm,
};
/* L3 CDP props */
@@ -458,13 +465,15 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat,
return true;
}
-static void l3_cdp_write_msr(unsigned int cos, uint32_t val,
- enum psr_type type)
+static uint32_t l3_cdp_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
wrmsrl(((type == PSR_TYPE_L3_DATA) ?
MSR_IA32_PSR_L3_MASK_DATA(cos) :
MSR_IA32_PSR_L3_MASK_CODE(cos)),
val);
+
+ return val;
}
static const struct feat_props l3_cdp_props = {
@@ -474,13 +483,16 @@ static const struct feat_props l3_cdp_props = {
.alt_type = PSR_TYPE_L3_CBM,
.get_feat_info = l3_cdp_get_feat_info,
.write_msr = l3_cdp_write_msr,
+ .check_val = cat_check_cbm,
};
/* L2 CAT props */
-static void l2_cat_write_msr(unsigned int cos, uint32_t val,
- enum psr_type type)
+static uint32_t l2_cat_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val);
+
+ return val;
}
static const struct feat_props l2_cat_props = {
@@ -489,6 +501,7 @@ static const struct feat_props l2_cat_props = {
.alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l2_cat_write_msr,
+ .check_val = cat_check_cbm,
};
/* MBA props */
@@ -509,9 +522,23 @@ static bool mba_get_feat_info(const struct feat_node *feat,
return true;
}
-static void mba_write_msr(unsigned int cos, uint32_t val,
- enum psr_type type)
+static uint32_t mba_write_msr(unsigned int cos, uint32_t val,
+ enum psr_type type)
{
+ wrmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
+
+ /* Read actual value set by hardware. */
+ rdmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
+
+ return val;
+}
+
+static bool mba_check_thrtl(const struct feat_node *feat, unsigned long thrtl)
+{
+ if ( thrtl > feat->mba.thrtl_max )
+ return false;
+
+ return true;
}
static const struct feat_props mba_props = {
@@ -520,6 +547,7 @@ static const struct feat_props mba_props = {
.alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = mba_get_feat_info,
.write_msr = mba_write_msr,
+ .check_val = mba_check_thrtl,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -964,7 +992,7 @@ static int insert_val_into_array(uint32_t val[],
if ( array_len < props->cos_num )
return -ENOSPC;
- if ( !psr_check_cbm(feat->cat.cbm_len, new_val) )
+ if ( !props->check_val(feat, new_val) )
return -EINVAL;
/*
@@ -1196,25 +1224,40 @@ static unsigned int get_socket_cpu(unsigned int socket)
struct cos_write_info
{
unsigned int cos;
- struct feat_node *feature;
+ struct feat_node **features;
const uint32_t *val;
- const struct feat_props *props;
+ unsigned int array_len;
+ const struct feat_props **props;
};
static void do_write_psr_msrs(void *data)
{
const struct cos_write_info *info = data;
- struct feat_node *feat = info->feature;
- const struct feat_props *props = info->props;
- unsigned int i, cos = info->cos, cos_num = props->cos_num;
+ unsigned int i, index = 0, array_len = info->array_len, cos = info->cos;
+ const uint32_t *val_array = info->val;
- for ( i = 0; i < cos_num; i++ )
+ for ( i = 0; i < ARRAY_SIZE(feat_props); i++ )
{
- if ( feat->cos_reg_val[cos * cos_num + i] != info->val[i] )
+ struct feat_node *feat = info->features[i];
+ const struct feat_props *props = info->props[i];
+ unsigned int cos_num, j;
+
+ if ( !feat || !props )
+ continue;
+
+ cos_num = props->cos_num;
+ if ( array_len < cos_num )
+ return;
+
+ for ( j = 0; j < cos_num; j++ )
{
- feat->cos_reg_val[cos * cos_num + i] = info->val[i];
- props->write_msr(cos, info->val[i], props->type[i]);
+ if ( feat->cos_reg_val[cos * cos_num + j] != val_array[index + j] )
+ feat->cos_reg_val[cos * cos_num + j] =
+ props->write_msr(cos, val_array[index + j], props->type[j]);
}
+
+ array_len -= cos_num;
+ index += cos_num;
}
}
@@ -1222,30 +1265,19 @@ static int write_psr_msrs(unsigned int socket, unsigned int cos,
const uint32_t val[], unsigned int array_len,
enum psr_feat_type feat_type)
{
- int ret;
struct psr_socket_info *info = get_socket_info(socket);
struct cos_write_info data =
{
.cos = cos,
- .feature = info->features[feat_type],
- .props = feat_props[feat_type],
+ .features = info->features,
+ .val = val,
+ .array_len = array_len,
+ .props = feat_props,
};
if ( cos > info->features[feat_type]->cos_max )
return -EINVAL;
- /* Skip to the feature's value head. */
- ret = skip_prior_features(&array_len, feat_type);
- if ( ret < 0 )
- return ret;
-
- val += ret;
-
- if ( array_len < feat_props[feat_type]->cos_num )
- return -ENOSPC;
-
- data.val = val;
-
if ( socket == cpu_to_socket(smp_processor_id()) )
do_write_psr_msrs(&data);
else
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 8be38cc..2710cda 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc {
#define XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_ALLOC_SET_MBA_THRTL 8
#define XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target; /* IN */
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 08/15] tools: create general interfaces to support psr allocation features
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (6 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 07/15] x86: implement set value flow " Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 10:04 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 09/15] tools: implement the new libxc get hw info interface Yi Sun
` (6 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch creates general interfaces in libxl to support all psr
allocation features.
Add 'LIBXL_HAVE_PSR_GENERIC' to indicate interface change.
Please note, the functionality cannot work until later patches
are applied.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- change 'LIBXL_HAVE_PSR_MBA' to 'LIBXL_HAVE_PSR_GENERIC'.
(suggested by Roger Pau Monné)
- 'typedef enum libxl_psr_cbm_type libxl_psr_type;' in libxl.h.
(suggested by Roger Pau Monné and Wei Liu)
- change 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly defined
interfaces.
(suggested by Roger Pau Monné)
v2:
- remove '_INFO' in 'libxl_psr_feat_type' and make corresponding
changes in 'libxl_psr_hw_info'.
(suggested by Chao Peng)
---
tools/libxl/libxl.h | 33 +++++++++++++++++++++++++++++++++
tools/libxl/libxl_psr.c | 25 +++++++++++++++++++++++++
tools/libxl/libxl_types.idl | 22 ++++++++++++++++++++++
3 files changed, 80 insertions(+)
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 484b5b7..9744087 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -931,6 +931,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src);
#define LIBXL_HAVE_PSR_L2_CAT 1
/*
+ * LIBXL_HAVE_PSR_GENERIC
+ *
+ * If this is defined, the Memory Bandwidth Allocation feature is supported.
+ */
+#define LIBXL_HAVE_PSR_GENERIC 1
+
+/*
* LIBXL_HAVE_MCA_CAPS
*
* If this is defined, setting MCA capabilities for HVM domain is supported.
@@ -2215,6 +2222,32 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
int libxl_psr_cat_get_l3_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
int *nr);
void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr);
+
+typedef enum libxl_psr_cbm_type libxl_psr_type;
+
+/*
+ * Function to set a domain's value. It operates on a single or multiple
+ * target(s) defined in 'target_map'. 'target_map' specifies all the sockets
+ * to be operated on.
+ */
+int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_type type, libxl_bitmap *target_map,
+ uint64_t val);
+/*
+ * Function to get a domain's cbm. It operates on a single 'target'.
+ * 'target' specifies which socket to be operated on.
+ */
+int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_type type, unsigned int target,
+ uint64_t *val);
+/*
+ * On success, the function returns an array of elements in 'info',
+ * and the length in 'nr'.
+ */
+int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
+ unsigned int *nr, libxl_psr_feat_type type,
+ unsigned int lvl);
+void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr);
#endif
/* misc */
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 197505a..4a6978e 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -428,6 +428,31 @@ void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr)
free(list);
}
+int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_type type, libxl_bitmap *target_map,
+ uint64_t val)
+{
+ return ERROR_FAIL;
+}
+
+int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_type type, unsigned int target,
+ uint64_t *val)
+{
+ return ERROR_FAIL;
+}
+
+int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
+ unsigned int *nr, libxl_psr_feat_type type,
+ unsigned int lvl)
+{
+ return ERROR_FAIL;
+}
+
+void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr)
+{
+}
+
/*
* Local variables:
* mode: C
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index 6e80d36..ab847f8 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -977,6 +977,7 @@ libxl_psr_cbm_type = Enumeration("psr_cbm_type", [
(2, "L3_CBM_CODE"),
(3, "L3_CBM_DATA"),
(4, "L2_CBM"),
+ (5, "MBA_THRTL"),
])
libxl_psr_cat_info = Struct("psr_cat_info", [
@@ -985,3 +986,24 @@ libxl_psr_cat_info = Struct("psr_cat_info", [
("cbm_len", uint32),
("cdp_enabled", bool),
])
+
+libxl_psr_feat_type = Enumeration("psr_feat_type", [
+ (1, "CAT"),
+ (2, "MBA"),
+ ])
+
+libxl_psr_hw_info = Struct("psr_hw_info", [
+ ("id", uint32),
+ ("u", KeyedUnion(None, libxl_psr_feat_type, "type",
+ [("cat", Struct(None, [
+ ("cos_max", uint32),
+ ("cbm_len", uint32),
+ ("cdp_enabled", bool),
+ ])),
+ ("mba", Struct(None, [
+ ("cos_max", uint32),
+ ("thrtl_max", uint32),
+ ("linear", bool),
+ ])),
+ ]))
+ ], dir=DIR_OUT)
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 09/15] tools: implement the new libxc get hw info interface
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (7 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 08/15] tools: create general interfaces to support psr allocation features Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 10:15 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 10/15] tools: implement the new libxl " Yi Sun
` (5 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements a new libxc get hw info interface and corresponding
data structures. It also changes libxl_psr.c to call this new interface.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
from name.
(suggested by Roger Pau Monné)
- remove 'info' from 'xc_cat_info' and 'xc_mba_info'.
(suggested by Roger Pau Monné)
- set errno in 'xc_psr_get_hw_info'.
(suggested by Roger Pau Monné)
- remove 'inline'.
(suggested by Roger Pau Monné)
- remove 'psr' from 'libxl__psr_feat_type_to_libxc_psr_feat_type' to make
function name shorter.
(suggested by Roger Pau Monné)
- check 'xc_type' in 'libxl_psr_cat_get_info'.
(suggested by Roger Pau Monné)
v2:
- split this patch out from a big patch in v1.
(suggested by Wei Liu)
- change 'CAT_INFO' and 'MBA_INFO' to 'CAT' and 'MBA'.
(suggested by Chao Peng)
---
tools/libxc/include/xenctrl.h | 30 +++++++++++++++++++++++---
tools/libxc/xc_psr.c | 49 ++++++++++++++++++++++++++++++++-----------
tools/libxl/libxl_psr.c | 38 +++++++++++++++++++++++++++++++--
3 files changed, 100 insertions(+), 17 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index c7710b8..bbdf8e2 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2458,6 +2458,31 @@ enum xc_psr_cat_type {
};
typedef enum xc_psr_cat_type xc_psr_cat_type;
+enum xc_psr_feat_type {
+ XC_PSR_FEAT_UNKNOWN,
+ XC_PSR_FEAT_CAT_L3,
+ XC_PSR_FEAT_CAT_L2,
+ XC_PSR_FEAT_MBA,
+};
+typedef enum xc_psr_feat_type xc_psr_feat_type;
+
+struct xc_psr_hw_info {
+ union {
+ struct {
+ uint32_t cos_max;
+ uint32_t cbm_len;
+ bool cdp_enabled;
+ } xc_cat;
+
+ struct {
+ uint32_t cos_max;
+ uint32_t thrtl_max;
+ bool linear;
+ } xc_mba;
+ } u;
+};
+typedef struct xc_psr_hw_info xc_psr_hw_info;
+
int xc_psr_cmt_attach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_detach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_get_domain_rmid(xc_interface *xch, uint32_t domid,
@@ -2479,9 +2504,8 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_cat_type type, uint32_t target,
uint64_t *data);
-int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
- uint32_t *cos_max, uint32_t *cbm_len,
- bool *cdp_enabled);
+int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
+ xc_psr_feat_type type, xc_psr_hw_info *hw_info);
int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 7e1c0d6..a8a750a 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -323,36 +323,61 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
return rc;
}
-int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
- uint32_t *cos_max, uint32_t *cbm_len, bool *cdp_enabled)
+int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
+ xc_psr_feat_type type, xc_psr_hw_info *hw_info)
{
int rc = -1;
DECLARE_SYSCTL;
+ if ( !hw_info )
+ {
+ errno = EINVAL;
+ return rc;
+ }
+
sysctl.cmd = XEN_SYSCTL_psr_alloc;
sysctl.u.psr_alloc.target = socket;
- switch ( lvl )
+ switch ( type )
{
- case 2:
+ case XC_PSR_FEAT_CAT_L2:
sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_l2_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_alloc.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_alloc.u.cat_info.cbm_len;
- *cdp_enabled = false;
+ hw_info->u.xc_cat.cos_max =
+ sysctl.u.psr_alloc.u.cat_info.cos_max;
+ hw_info->u.xc_cat.cbm_len =
+ sysctl.u.psr_alloc.u.cat_info.cbm_len;
+ hw_info->u.xc_cat.cdp_enabled = false;
}
break;
- case 3:
+ case XC_PSR_FEAT_CAT_L3:
sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_l3_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_alloc.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_alloc.u.cat_info.cbm_len;
- *cdp_enabled = sysctl.u.psr_alloc.u.cat_info.flags &
- XEN_SYSCTL_PSR_ALLOC_L3_CDP;
+ hw_info->u.xc_cat.cos_max =
+ sysctl.u.psr_alloc.u.cat_info.cos_max;
+ hw_info->u.xc_cat.cbm_len =
+ sysctl.u.psr_alloc.u.cat_info.cbm_len;
+ hw_info->u.xc_cat.cdp_enabled =
+ sysctl.u.psr_alloc.u.cat_info.flags &
+ XEN_SYSCTL_PSR_ALLOC_L3_CDP;
+ }
+ break;
+ case XC_PSR_FEAT_MBA:
+ sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_mba_info;
+ rc = xc_sysctl(xch, &sysctl);
+ if ( !rc )
+ {
+ hw_info->u.xc_mba.cos_max =
+ sysctl.u.psr_alloc.u.mba_info.cos_max;
+ hw_info->u.xc_mba.thrtl_max =
+ sysctl.u.psr_alloc.u.mba_info.thrtl_max;
+ hw_info->u.xc_mba.linear =
+ sysctl.u.psr_alloc.u.mba_info.flags &
+ XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
}
break;
default:
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 4a6978e..dd412cc 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -361,6 +361,27 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
return rc;
}
+static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
+ libxl_psr_feat_type type, unsigned int lvl)
+{
+ xc_psr_feat_type xc_type = XC_PSR_FEAT_UNKNOWN;
+
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT:
+ if (lvl == 3)
+ xc_type = XC_PSR_FEAT_CAT_L3;
+ if (lvl == 2)
+ xc_type = XC_PSR_FEAT_CAT_L2;
+ break;
+ case LIBXL_PSR_FEAT_TYPE_MBA:
+ xc_type = XC_PSR_FEAT_MBA;
+ default:
+ break;
+ }
+
+ return xc_type;
+}
+
int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
unsigned int *nr, unsigned int lvl)
{
@@ -369,6 +390,8 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
int i = 0, socketid, nr_sockets;
libxl_bitmap socketmap;
libxl_psr_cat_info *ptr;
+ xc_psr_hw_info hw_info;
+ xc_psr_feat_type xc_type;
libxl_bitmap_init(&socketmap);
@@ -385,16 +408,27 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
goto out;
}
+ xc_type = libxl__feat_type_to_libxc_feat_type(LIBXL_PSR_FEAT_TYPE_CAT, lvl);
+ if (xc_type == XC_PSR_FEAT_UNKNOWN) {
+ LOG(ERROR, "feature type or lvl is wrong");
+ rc = ERROR_FAIL;
+ goto out;
+ }
+
ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
libxl_for_each_set_bit(socketid, socketmap) {
ptr[i].id = socketid;
- if (xc_psr_cat_get_info(ctx->xch, socketid, lvl, &ptr[i].cos_max,
- &ptr[i].cbm_len, &ptr[i].cdp_enabled)) {
+ if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
rc = ERROR_FAIL;
free(ptr);
goto out;
}
+
+ ptr[i].cos_max = hw_info.u.xc_cat.cos_max;
+ ptr[i].cbm_len = hw_info.u.xc_cat.cbm_len;
+ ptr[i].cdp_enabled = hw_info.u.xc_cat.cdp_enabled;
+
i++;
}
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 10/15] tools: implement the new libxl get hw info interface
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (8 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 09/15] tools: implement the new libxc get hw info interface Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 10:28 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 11/15] tools: implement the new xl " Yi Sun
` (4 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements the new libxl get hw info interface,
'libxl_psr_get_hw_info', which is suitable to all psr allocation
features. It also implements corresponding list free function,
'libxl_psr_hw_info_list_free' and make 'libxl_psr_cat_get_info' to call
'libxl_psr_get_hw_info' to avoid redundant codes in libxl_psr.c.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- remove casting.
(suggested by Roger Pau Monné)
- remove inline.
(suggested by Roger Pau Monné)
- change 'libxc__psr_hw_info_to_libxl_psr_hw_info' to
'libxl__xc_hw_info_to_libxl_hw_info'.
(suggested by Roger Pau Monné)
- remove '_hw' from parameter names.
(suggested by Roger Pau Monné)
- change some 'LOGE' to 'LOG'.
(suggested by Roger Pau Monné)
- check returned 'xc_type' and remove redundant 'lvl' check.
(suggested by Roger Pau Monné)
v2:
- split this patch out from a big patch in v1.
(suggested by Wei Liu)
- change 'CAT_INFO'/'MBA_INFO' to 'CAT' and 'MBA. Also the libxl structure
name 'cat_info'/'mba_info' is changed to 'cat'/'mba'.
(suggested by Chao Peng)
- call 'libxl_psr_hw_info_list_free' in 'libxl_psr_cat_get_info' to free
allocated resources.
(suggested by Chao Peng)
---
tools/libxl/libxl_psr.c | 145 ++++++++++++++++++++++++++++++++++++------------
1 file changed, 108 insertions(+), 37 deletions(-)
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index dd412cc..d534ec2 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -382,60 +382,49 @@ static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
return xc_type;
}
+static int libxl__hw_info_to_libxl_cat_info(
+ libxl_psr_feat_type type, libxl_psr_hw_info *hw_info,
+ libxl_psr_cat_info *cat_info)
+{
+ if (type != LIBXL_PSR_FEAT_TYPE_CAT)
+ return ERROR_INVAL;
+
+ cat_info->id = hw_info->id;
+ cat_info->cos_max = hw_info->u.cat.cos_max;
+ cat_info->cbm_len = hw_info->u.cat.cbm_len;
+ cat_info->cdp_enabled = hw_info->u.cat.cdp_enabled;
+
+ return 0;
+}
+
int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
unsigned int *nr, unsigned int lvl)
{
GC_INIT(ctx);
int rc;
- int i = 0, socketid, nr_sockets;
- libxl_bitmap socketmap;
+ unsigned int i;
+ libxl_psr_hw_info *hw_info;
libxl_psr_cat_info *ptr;
- xc_psr_hw_info hw_info;
- xc_psr_feat_type xc_type;
-
- libxl_bitmap_init(&socketmap);
- rc = libxl__count_physical_sockets(gc, &nr_sockets);
- if (rc) {
- LOGE(ERROR, "failed to get system socket count");
+ rc = libxl_psr_get_hw_info(ctx, &hw_info, nr, LIBXL_PSR_FEAT_TYPE_CAT, lvl);
+ if (rc)
goto out;
- }
- libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
- rc = libxl_get_online_socketmap(ctx, &socketmap);
- if (rc < 0) {
- LOGE(ERROR, "failed to get available sockets");
- goto out;
- }
-
- xc_type = libxl__feat_type_to_libxc_feat_type(LIBXL_PSR_FEAT_TYPE_CAT, lvl);
- if (xc_type == XC_PSR_FEAT_UNKNOWN) {
- LOG(ERROR, "feature type or lvl is wrong");
- rc = ERROR_FAIL;
- goto out;
- }
+ ptr = libxl__malloc(NOGC, *nr * sizeof(libxl_psr_cat_info));
- ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
-
- libxl_for_each_set_bit(socketid, socketmap) {
- ptr[i].id = socketid;
- if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
+ for (i = 0; i < *nr; i++) {
+ if (libxl__hw_info_to_libxl_cat_info(LIBXL_PSR_FEAT_TYPE_CAT,
+ &hw_info[i], &ptr[i])) {
+ libxl_psr_hw_info_list_free(hw_info, *nr);
rc = ERROR_FAIL;
free(ptr);
goto out;
}
-
- ptr[i].cos_max = hw_info.u.xc_cat.cos_max;
- ptr[i].cbm_len = hw_info.u.xc_cat.cbm_len;
- ptr[i].cdp_enabled = hw_info.u.xc_cat.cdp_enabled;
-
- i++;
}
*info = ptr;
- *nr = i;
+ libxl_psr_hw_info_list_free(hw_info, *nr);
out:
- libxl_bitmap_dispose(&socketmap);
GC_FREE;
return rc;
}
@@ -476,15 +465,97 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
return ERROR_FAIL;
}
+static int libxl__xc_hw_info_to_libxl_hw_info(
+ libxl_psr_feat_type type, xc_psr_hw_info *xc_info,
+ libxl_psr_hw_info *xl_info)
+{
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT:
+ xl_info->u.cat.cos_max = xc_info->u.xc_cat.cos_max;
+ xl_info->u.cat.cbm_len = xc_info->u.xc_cat.cbm_len;
+ xl_info->u.cat.cdp_enabled = xc_info->u.xc_cat.cdp_enabled;
+ break;
+ case LIBXL_PSR_FEAT_TYPE_MBA:
+ xl_info->u.mba.cos_max = xc_info->u.xc_mba.cos_max;
+ xl_info->u.mba.thrtl_max = xc_info->u.xc_mba.thrtl_max;
+ xl_info->u.mba.linear = xc_info->u.xc_mba.linear;
+ break;
+ default:
+ return ERROR_INVAL;
+ }
+
+ return 0;
+}
+
int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
unsigned int *nr, libxl_psr_feat_type type,
unsigned int lvl)
{
- return ERROR_FAIL;
+ GC_INIT(ctx);
+ int rc, nr_sockets;
+ unsigned int i = 0, socketid;
+ libxl_bitmap socketmap;
+ libxl_psr_hw_info *ptr;
+ xc_psr_feat_type xc_type;
+ xc_psr_hw_info hw_info;
+
+ libxl_bitmap_init(&socketmap);
+
+ xc_type = libxl__feat_type_to_libxc_feat_type(type, lvl);
+ if (xc_type == XC_PSR_FEAT_UNKNOWN) {
+ LOG(ERROR, "feature type or lvl is wrong");
+ rc = ERROR_FAIL;
+ goto out;
+ }
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOG(ERROR, "failed to get system socket count");
+ goto out;
+ }
+
+ libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
+ rc = libxl_get_online_socketmap(ctx, &socketmap);
+ if (rc < 0) {
+ LOGE(ERROR, "failed to get available sockets");
+ goto out;
+ }
+
+ ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_hw_info));
+
+ libxl_for_each_set_bit(socketid, socketmap) {
+ ptr[i].id = socketid;
+ if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
+ rc = ERROR_FAIL;
+ free(ptr);
+ goto out;
+ }
+
+ if (libxl__xc_hw_info_to_libxl_hw_info(type, &hw_info, &ptr[i])) {
+ LOGE(ERROR, "Input type %d is wrong!\n", type);
+ rc = ERROR_FAIL;
+ free(ptr);
+ goto out;
+ }
+
+ i++;
+ }
+
+ *info = ptr;
+ *nr = i;
+out:
+ libxl_bitmap_dispose(&socketmap);
+ GC_FREE;
+ return rc;
}
void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr)
{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ libxl_psr_hw_info_dispose(&list[i]);
+ free(list);
}
/*
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 11/15] tools: implement the new xl get hw info interface
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (9 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 10/15] tools: implement the new libxl " Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 10:32 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
` (3 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements a new xl get HW info interface. A new argument
is added for psr-hwinfo command to get and show MBA HW info.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- change the format string of printf in 'psr_mba_hwinfo'.
(suggested by Roger Pau Monné)
- add 'const' for 'opts[]' in 'main_psr_hwinfo'.
(suggested by Roger Pau Monné)
v2:
- split out this patch from a big patch in v1.
(suggested by Wei Liu)
- change 'MBA_INFO' to 'MBA'. Also, change 'mba_info' to 'mba'.
(suggested by Chao Peng)
---
tools/xl/xl_cmdtable.c | 1 +
tools/xl/xl_psr.c | 40 +++++++++++++++++++++++++++++++++++++---
2 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 6baaed2..a01245d 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -524,6 +524,7 @@ struct cmd_spec cmd_table[] = {
"[options]",
"-m, --cmt Show Cache Monitoring Technology (CMT) hardware info\n"
"-a, --cat Show Cache Allocation Technology (CAT) hardware info\n"
+ "-b, --mba Show Memory Bandwidth Allocation (MBA) hardware info\n"
},
{ "psr-cmt-attach",
&main_psr_cmt_attach, 0, 1,
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index ef00048..40269b4 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -475,6 +475,32 @@ static int psr_l2_cat_hwinfo(void)
return rc;
}
+static int psr_mba_hwinfo(void)
+{
+ int rc;
+ unsigned int i, nr;
+ libxl_psr_hw_info *info;
+
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_MBA, 0);
+ if (rc)
+ return rc;
+
+ printf("Memory Bandwidth Allocation (MBA):\n");
+
+ for (i = 0; i < nr; i++) {
+ printf("Socket ID : %u\n", info[i].id);
+ printf("Linear Mode : %s\n",
+ info[i].u.mba.linear ? "Enabled" : "Disabled");
+ printf("Maximum COS : %u\n", info[i].u.mba.cos_max);
+ printf("Maximum Throttling Value: %u\n", info[i].u.mba.thrtl_max);
+ printf("Default Throttling Value: %u\n", 0);
+ }
+
+ libxl_psr_hw_info_list_free(info, nr);
+ return rc;
+}
+
int main_psr_cat_cbm_set(int argc, char **argv)
{
uint32_t domid;
@@ -593,20 +619,24 @@ int main_psr_cat_show(int argc, char **argv)
int main_psr_hwinfo(int argc, char **argv)
{
int opt, ret = 0;
- bool all = true, cmt = false, cat = false;
- static struct option opts[] = {
+ bool all = true, cmt = false, cat = false, mba = false;
+ static const struct option opts[] = {
{"cmt", 0, 0, 'm'},
{"cat", 0, 0, 'a'},
+ {"mba", 0, 0, 'b'},
COMMON_LONG_OPTS
};
- SWITCH_FOREACH_OPT(opt, "ma", opts, "psr-hwinfo", 0) {
+ SWITCH_FOREACH_OPT(opt, "mab", opts, "psr-hwinfo", 0) {
case 'm':
all = false; cmt = true;
break;
case 'a':
all = false; cat = true;
break;
+ case 'b':
+ all = false; mba = true;
+ break;
}
if (!ret && (all || cmt))
@@ -619,6 +649,10 @@ int main_psr_hwinfo(int argc, char **argv)
if (all || cat)
ret = psr_l2_cat_hwinfo();
+ /* MBA is independent of CMT and CAT */
+ if (all || mba)
+ ret = psr_mba_hwinfo();
+
return ret;
}
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type'
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (10 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 11/15] tools: implement the new xl " Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 10:34 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command Yi Sun
` (2 subsequent siblings)
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch renames 'xc_psr_cat_type' to 'xc_psr_type' so that
the structure name is common for all allocation features.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Chao Peng <chao.p.peng@linux.intel.com>
---
v3:
- change 'xc_psr_val_type' to 'xc_psr_type'.
(suggested by Roger Pau Monné)
---
tools/libxc/include/xenctrl.h | 8 ++++----
tools/libxc/xc_psr.c | 4 ++--
tools/libxl/libxl_psr.c | 12 ++++++------
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index bbdf8e2..63b92d2 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2450,13 +2450,13 @@ enum xc_psr_cmt_type {
};
typedef enum xc_psr_cmt_type xc_psr_cmt_type;
-enum xc_psr_cat_type {
+enum xc_psr_type {
XC_PSR_CAT_L3_CBM = 1,
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
XC_PSR_CAT_L2_CBM = 4,
};
-typedef enum xc_psr_cat_type xc_psr_cat_type;
+typedef enum xc_psr_type xc_psr_type;
enum xc_psr_feat_type {
XC_PSR_FEAT_UNKNOWN,
@@ -2499,10 +2499,10 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
int xc_psr_cmt_enabled(xc_interface *xch);
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_type type, uint32_t target,
uint64_t data);
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_type type, uint32_t target,
uint64_t *data);
int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
xc_psr_feat_type type, xc_psr_hw_info *hw_info);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index a8a750a..80642a2 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -249,7 +249,7 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_type type, uint32_t target,
uint64_t data)
{
DECLARE_DOMCTL;
@@ -284,7 +284,7 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
}
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_type type, uint32_t target,
uint64_t *data)
{
int rc;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index d534ec2..c8d2921 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -303,11 +303,11 @@ out:
return rc;
}
-static inline xc_psr_cat_type libxl__psr_cbm_type_to_libxc_psr_cat_type(
+static inline xc_psr_type libxl__psr_cbm_type_to_libxc_psr_type(
libxl_psr_cbm_type type)
{
- BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_cat_type));
- return (xc_psr_cat_type)type;
+ BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_type));
+ return (xc_psr_type)type;
}
int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
@@ -325,12 +325,12 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
}
libxl_for_each_set_bit(socketid, *target_map) {
- xc_psr_cat_type xc_type;
+ xc_psr_type xc_type;
if (socketid >= nr_sockets)
break;
- xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
+ xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
socketid, cbm)) {
libxl__psr_cat_log_err_msg(gc, errno);
@@ -349,7 +349,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
{
GC_INIT(ctx);
int rc = 0;
- xc_psr_cat_type xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
+ xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
target, cbm_r)) {
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (11 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 11:02 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 14/15] tools: implement new generic set value interface and MBA set " Yi Sun
2017-09-05 9:32 ` [PATCH v3 15/15] docs: add MBA description in docs Yi Sun
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements generic get value interfaces in libxc and libxl.
It also refactors the get value flow in xl to make it be suitable for all
allocation features. Based on that, a new MBA get value command is added in xl.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
v3:
- replace 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly defined
interfaces.
(suggested by Roger Pau Monné)
v2:
- change 'CAT_INFO'/'MBA_INFO' to 'CAT'/'MBA'. The related structure names
are changed too.
(suggested by Chao Peng)
---
tools/libxc/include/xenctrl.h | 7 +-
tools/libxc/xc_psr.c | 9 +-
tools/libxl/libxl_psr.c | 59 +++++++++-----
tools/xl/xl.h | 1 +
tools/xl/xl_cmdtable.c | 5 ++
tools/xl/xl_psr.c | 185 ++++++++++++++++++++++++++++++------------
6 files changed, 184 insertions(+), 82 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 63b92d2..eef06be 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2455,6 +2455,7 @@ enum xc_psr_type {
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
XC_PSR_CAT_L2_CBM = 4,
+ XC_PSR_MBA_THRTL = 5,
};
typedef enum xc_psr_type xc_psr_type;
@@ -2501,9 +2502,9 @@ int xc_psr_cmt_enabled(xc_interface *xch);
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_type type, uint32_t target,
uint64_t data);
-int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_type type, uint32_t target,
- uint64_t *data);
+int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_type type, uint32_t target,
+ uint64_t *data);
int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
xc_psr_feat_type type, xc_psr_hw_info *hw_info);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 80642a2..2f0eed9 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -283,9 +283,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
return do_domctl(xch, &domctl);
}
-int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_type type, uint32_t target,
- uint64_t *data)
+int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_type type, uint32_t target,
+ uint64_t *data)
{
int rc;
DECLARE_DOMCTL;
@@ -305,6 +305,9 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
case XC_PSR_CAT_L2_CBM:
cmd = XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM;
break;
+ case XC_PSR_MBA_THRTL:
+ cmd = XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL;
+ break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index c8d2921..78d5bc5 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -71,16 +71,30 @@ static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
LOGE(ERROR, "%s", msg);
}
-static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
+static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
+ int err,
+ libxl_psr_type type)
{
+ /*
+ * Index is 'libxl_psr_type' so we set two 'CDP' to correspond to
+ * DATA and CODE.
+ */
+ const char * const feat_name[6] = {
+ "UNKNOWN",
+ "L3 CAT",
+ "CDP",
+ "CDP",
+ "L2 CAT",
+ "MBA",
+ };
char *msg;
switch (err) {
case ENODEV:
- msg = "CAT is not supported in this system";
+ msg = "is not supported in this system";
break;
case ENOENT:
- msg = "CAT is not enabled on the socket";
+ msg = "is not enabled on the socket";
break;
case EOVERFLOW:
msg = "no free COS available";
@@ -106,7 +120,7 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
return;
}
- LOGE(ERROR, "%s", msg);
+ LOGE(ERROR, "%s: %s", feat_name[type], msg);
}
static int libxl__pick_socket_cpu(libxl__gc *gc, uint32_t socketid)
@@ -303,10 +317,10 @@ out:
return rc;
}
-static inline xc_psr_type libxl__psr_cbm_type_to_libxc_psr_type(
- libxl_psr_cbm_type type)
+static inline xc_psr_type libxl__psr_type_to_libxc_psr_type(
+ libxl_psr_type type)
{
- BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_type));
+ BUILD_BUG_ON(sizeof(libxl_psr_type) != sizeof(xc_psr_type));
return (xc_psr_type)type;
}
@@ -330,10 +344,10 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
if (socketid >= nr_sockets)
break;
- xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
+ xc_type = libxl__psr_type_to_libxc_psr_type(type);
if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
socketid, cbm)) {
- libxl__psr_cat_log_err_msg(gc, errno);
+ libxl__psr_alloc_log_err_msg(gc, errno, type);
rc = ERROR_FAIL;
}
}
@@ -347,18 +361,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, uint32_t target,
uint64_t *cbm_r)
{
- GC_INIT(ctx);
- int rc = 0;
- xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
-
- if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
- target, cbm_r)) {
- libxl__psr_cat_log_err_msg(gc, errno);
- rc = ERROR_FAIL;
- }
-
- GC_FREE;
- return rc;
+ return libxl_psr_get_val(ctx, domid, type, target, cbm_r);
}
static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
@@ -462,7 +465,19 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
libxl_psr_type type, unsigned int target,
uint64_t *val)
{
- return ERROR_FAIL;
+ GC_INIT(ctx);
+ int rc = 0;
+
+ xc_psr_type xc_type = libxl__psr_type_to_libxc_psr_type(type);
+
+ if (xc_psr_get_domain_data(ctx->xch, domid, xc_type,
+ target, val)) {
+ libxl__psr_alloc_log_err_msg(gc, errno, type);
+ rc = ERROR_FAIL;
+ }
+
+ GC_FREE;
+ return rc;
}
static int libxl__xc_hw_info_to_libxl_hw_info(
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 8d7b957..3389df9 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -204,6 +204,7 @@ int main_psr_cmt_detach(int argc, char **argv);
int main_psr_cmt_show(int argc, char **argv);
int main_psr_cat_cbm_set(int argc, char **argv);
int main_psr_cat_show(int argc, char **argv);
+int main_psr_mba_show(int argc, char **argv);
#endif
int main_qemu_monitor_command(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index a01245d..cdc2349 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -560,6 +560,11 @@ struct cmd_spec cmd_table[] = {
"[options] <Domain>",
"-l <level> Specify the cache level to process, otherwise L3 cache is processed\n"
},
+ { "psr-mba-show",
+ &main_psr_mba_show, 0, 1,
+ "Show Memory Bandwidth Allocation information",
+ "<Domain>",
+ },
#endif
{ "usbctrl-attach",
&main_usbctrl_attach, 0, 1,
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index 40269b4..46b7788 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -327,19 +327,27 @@ out:
return rc;
}
-static void psr_cat_print_one_domain_cbm_type(uint32_t domid, uint32_t socketid,
- libxl_psr_cbm_type type)
+static void psr_print_one_domain_val_type(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_type type)
{
- uint64_t cbm;
+ uint64_t val;
- if (!libxl_psr_cat_get_cbm(ctx, domid, type, socketid, &cbm))
- printf("%#16"PRIx64, cbm);
+ if (!libxl_psr_get_val(ctx, domid, type, info->id, &val))
+ {
+ if (type == LIBXL_PSR_CBM_TYPE_MBA_THRTL && info->u.mba.linear)
+ printf("%16"PRIu64, val);
+ else
+ printf("%#16"PRIx64, val);
+ }
else
printf("%16s", "error");
}
-static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
- bool cdp_enabled, unsigned int lvl)
+static void psr_print_one_domain_val(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
char *domain_name;
@@ -347,106 +355,154 @@ static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
printf("%5d%25s", domid, domain_name);
free(domain_name);
- switch (lvl) {
- case 3:
- if (!cdp_enabled) {
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT:
+ switch (lvl) {
+ case 3:
+ if (!info->u.cat.cdp_enabled) {
+ psr_print_one_domain_val_type(domid, info,
LIBXL_PSR_CBM_TYPE_L3_CBM);
- } else {
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ } else {
+ psr_print_one_domain_val_type(domid, info,
LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ psr_print_one_domain_val_type(domid, info,
LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
- }
- break;
- case 2:
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ }
+ break;
+
+ case 2:
+ psr_print_one_domain_val_type(domid, info,
LIBXL_PSR_CBM_TYPE_L2_CBM);
+ break;
+
+ default:
+ printf("Input lvl %d is wrong!", lvl);
+ }
break;
- default:
- printf("Input lvl %d is wrong!", lvl);
+
+ case LIBXL_PSR_FEAT_TYPE_MBA:
+ psr_print_one_domain_val_type(domid, info,
+ LIBXL_PSR_CBM_TYPE_MBA_THRTL);
break;
}
printf("\n");
}
-static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socketid,
- bool cdp_enabled, unsigned int lvl)
+static int psr_print_domain_val(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
int i, nr_domains;
libxl_dominfo *list;
if (domid != INVALID_DOMID) {
- psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled, lvl);
+ psr_print_one_domain_val(domid, info, type, lvl);
return 0;
}
if (!(list = libxl_list_domain(ctx, &nr_domains))) {
- fprintf(stderr, "Failed to get domain list for cbm display\n");
- return -1;
+ fprintf(stderr, "Failed to get domain list for value display\n");
+ return EXIT_FAILURE;
}
for (i = 0; i < nr_domains; i++)
- psr_cat_print_one_domain_cbm(list[i].domid, socketid, cdp_enabled, lvl);
+ psr_print_one_domain_val(list[i].domid, info, type, lvl);
libxl_dominfo_list_free(list, nr_domains);
return 0;
}
-static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
- unsigned int lvl)
+static int psr_print_socket(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
- int rc;
- uint32_t l3_cache_size;
-
printf("%-16s: %u\n", "Socket ID", info->id);
- /* So far, CMT only supports L3 cache. */
- if (lvl == 3) {
- rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
- if (rc) {
- fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
- info->id);
- return -1;
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT:
+ {
+ int rc;
+ uint32_t l3_cache_size;
+
+ /* So far, CMT only supports L3 cache. */
+ if (lvl == 3) {
+ rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
+ if (rc) {
+ fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
+ info->id);
+ return -1;
+ }
+ printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
}
- printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
+
+ printf("%-16s: %#llx\n", "Default CBM",
+ (1ull << info->u.cat.cbm_len) - 1);
+ if (info->u.cat.cdp_enabled)
+ printf("%5s%25s%16s%16s\n", "ID", "NAME", "CBM (code)", "CBM (data)");
+ else
+ printf("%5s%25s%16s\n", "ID", "NAME", "CBM");
+
+ break;
}
- printf("%-16s: %#llx\n", "Default CBM", (1ull << info->cbm_len) - 1);
- if (info->cdp_enabled)
- printf("%5s%25s%16s%16s\n", "ID", "NAME", "CBM (code)", "CBM (data)");
- else
- printf("%5s%25s%16s\n", "ID", "NAME", "CBM");
+ case LIBXL_PSR_FEAT_TYPE_MBA:
+ printf("%-16s: %u\n", "Default THRTL", 0);
+ printf("%5s%25s%16s\n", "ID", "NAME", "THRTL");
+ break;
- return psr_cat_print_domain_cbm(domid, info->id, info->cdp_enabled, lvl);
+ default:
+ fprintf(stderr, "Input feature type %d is wrong\n", type);
+ return EXIT_FAILURE;
+ }
+
+ return psr_print_domain_val(domid, info, type, lvl);
}
-static int psr_cat_show(uint32_t domid, unsigned int lvl)
+static int psr_val_show(uint32_t domid,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
unsigned int i, nr;
int rc;
- libxl_psr_cat_info *info;
+ libxl_psr_hw_info *info;
- if (lvl != 2 && lvl != 3) {
- fprintf(stderr, "Input lvl %d is wrong\n", lvl);
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT:
+ if (lvl != 2 && lvl != 3) {
+ fprintf(stderr, "Input lvl %d is wrong\n", lvl);
+ return EXIT_FAILURE;
+ }
+ break;
+
+ case LIBXL_PSR_FEAT_TYPE_MBA:
+ if (lvl) {
+ fprintf(stderr, "Input lvl %d is wrong\n", lvl);
+ return EXIT_FAILURE;
+ }
+ break;
+
+ default:
+ fprintf(stderr, "Input feature type %d is wrong\n", type);
return EXIT_FAILURE;
}
- rc = libxl_psr_cat_get_info(ctx, &info, &nr, lvl);
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr, type, lvl);
if (rc) {
- fprintf(stderr, "Failed to get %s cat info\n", (lvl == 3)?"L3":"L2");
+ fprintf(stderr, "Failed to get info\n");
return rc;
}
for (i = 0; i < nr; i++) {
- rc = psr_cat_print_socket(domid, info + i, lvl);
+ rc = psr_print_socket(domid, info + i, type, lvl);
if (rc)
goto out;
}
out:
- libxl_psr_cat_info_list_free(info, nr);
+ libxl_psr_hw_info_list_free(info, nr);
return rc;
}
@@ -475,6 +531,27 @@ static int psr_l2_cat_hwinfo(void)
return rc;
}
+int main_psr_mba_show(int argc, char **argv)
+{
+ int opt;
+ uint32_t domid;
+
+ SWITCH_FOREACH_OPT(opt, "", NULL, "psr-mba-show", 0) {
+ /* No options */
+ }
+
+ if (optind >= argc)
+ domid = INVALID_DOMID;
+ else if (optind == argc - 1)
+ domid = find_domain(argv[optind]);
+ else {
+ help("psr-mba-show");
+ return 2;
+ }
+
+ return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_MBA, 0);
+}
+
static int psr_mba_hwinfo(void)
{
int rc;
@@ -613,7 +690,7 @@ int main_psr_cat_show(int argc, char **argv)
return 2;
}
- return psr_cat_show(domid, lvl);
+ return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_CAT, lvl);
}
int main_psr_hwinfo(int argc, char **argv)
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 14/15] tools: implement new generic set value interface and MBA set value command
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (12 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 11:30 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 15/15] docs: add MBA description in docs Yi Sun
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch implements new generic set value interfaces in libxc and libxl.
These interfaces are suitable for all allocation features. It also adds a
new MBA set value command in xl.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v3:
- add 'const' for 'opts[]' in 'main_psr_mba_set'.
(suggested by Roger Pau Monné)
- replace 'libxl_psr_cbm_type' to 'libxl_psr_type' for newly defined
interfaces.
(suggested by Roger Pau Monné)
---
tools/libxc/include/xenctrl.h | 6 ++---
tools/libxc/xc_psr.c | 9 ++++---
tools/libxl/libxl_psr.c | 56 +++++++++++++++++++++----------------------
tools/xl/xl.h | 1 +
tools/xl/xl_cmdtable.c | 6 +++++
tools/xl/xl_psr.c | 55 ++++++++++++++++++++++++++++++++++++++++++
6 files changed, 99 insertions(+), 34 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index eef06be..21dac2f 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2499,9 +2499,9 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
uint64_t *tsc);
int xc_psr_cmt_enabled(xc_interface *xch);
-int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_type type, uint32_t target,
- uint64_t data);
+int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_type type, uint32_t target,
+ uint64_t data);
int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_type type, uint32_t target,
uint64_t *data);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 2f0eed9..e53b5f5 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -248,9 +248,9 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
-int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_type type, uint32_t target,
- uint64_t data)
+int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_type type, uint32_t target,
+ uint64_t data)
{
DECLARE_DOMCTL;
uint32_t cmd;
@@ -269,6 +269,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
case XC_PSR_CAT_L2_CBM:
cmd = XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM;
break;
+ case XC_PSR_MBA_THRTL:
+ cmd = XEN_DOMCTL_PSR_ALLOC_SET_MBA_THRTL;
+ break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 78d5bc5..d3c3d42 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -328,33 +328,7 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, libxl_bitmap *target_map,
uint64_t cbm)
{
- GC_INIT(ctx);
- int rc;
- int socketid, nr_sockets;
-
- rc = libxl__count_physical_sockets(gc, &nr_sockets);
- if (rc) {
- LOGED(ERROR, domid, "failed to get system socket count");
- goto out;
- }
-
- libxl_for_each_set_bit(socketid, *target_map) {
- xc_psr_type xc_type;
-
- if (socketid >= nr_sockets)
- break;
-
- xc_type = libxl__psr_type_to_libxc_psr_type(type);
- if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
- socketid, cbm)) {
- libxl__psr_alloc_log_err_msg(gc, errno, type);
- rc = ERROR_FAIL;
- }
- }
-
-out:
- GC_FREE;
- return rc;
+ return libxl_psr_set_val(ctx, domid, type, target_map, cbm);
}
int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
@@ -458,7 +432,33 @@ int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
libxl_psr_type type, libxl_bitmap *target_map,
uint64_t val)
{
- return ERROR_FAIL;
+ GC_INIT(ctx);
+ int rc;
+ int socketid, nr_sockets;
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOG(ERROR, "failed to get system socket count");
+ goto out;
+ }
+
+ libxl_for_each_set_bit(socketid, *target_map) {
+ xc_psr_type xc_type;
+
+ if (socketid >= nr_sockets)
+ break;
+
+ xc_type = libxl__psr_type_to_libxc_psr_type(type);
+ if (xc_psr_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, val)) {
+ libxl__psr_alloc_log_err_msg(gc, errno, type);
+ rc = ERROR_FAIL;
+ }
+ }
+
+out:
+ GC_FREE;
+ return rc;
}
int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 3389df9..3f99b6b 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -204,6 +204,7 @@ int main_psr_cmt_detach(int argc, char **argv);
int main_psr_cmt_show(int argc, char **argv);
int main_psr_cat_cbm_set(int argc, char **argv);
int main_psr_cat_show(int argc, char **argv);
+int main_psr_mba_set(int argc, char **argv);
int main_psr_mba_show(int argc, char **argv);
#endif
int main_qemu_monitor_command(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index cdc2349..9d45d3b 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -560,6 +560,12 @@ struct cmd_spec cmd_table[] = {
"[options] <Domain>",
"-l <level> Specify the cache level to process, otherwise L3 cache is processed\n"
},
+ { "psr-mba-set",
+ &main_psr_mba_set, 0, 1,
+ "Set throttling value (THRTL) for a domain",
+ "[options] <Domain> <THRTL>",
+ "-s <socket> Specify the socket to process, otherwise all sockets are processed\n"
+ },
{ "psr-mba-show",
&main_psr_mba_show, 0, 1,
"Show Memory Bandwidth Allocation information",
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index 46b7788..a648b1a 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -552,6 +552,61 @@ int main_psr_mba_show(int argc, char **argv)
return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_MBA, 0);
}
+int main_psr_mba_set(int argc, char **argv)
+{
+ uint32_t domid;
+ libxl_psr_type type;
+ uint64_t thrtl;
+ int ret, opt = 0;
+ libxl_bitmap target_map;
+ char *value;
+ libxl_string_list socket_list;
+ unsigned long start, end;
+ unsigned int i, j, len;
+
+ static const struct option opts[] = {
+ {"socket", 1, 0, 's'},
+ COMMON_LONG_OPTS
+ };
+
+ libxl_socket_bitmap_alloc(ctx, &target_map, 0);
+ libxl_bitmap_set_none(&target_map);
+
+ SWITCH_FOREACH_OPT(opt, "s:", opts, "psr-mba-set", 0) {
+ case 's':
+ trim(isspace, optarg, &value);
+ split_string_into_string_list(value, ",", &socket_list);
+ len = libxl_string_list_length(&socket_list);
+ for (i = 0; i < len; i++) {
+ parse_range(socket_list[i], &start, &end);
+ for (j = start; j <= end; j++)
+ libxl_bitmap_set(&target_map, j);
+ }
+
+ libxl_string_list_dispose(&socket_list);
+ free(value);
+ break;
+ }
+
+ type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
+
+ if (libxl_bitmap_is_empty(&target_map))
+ libxl_bitmap_set_any(&target_map);
+
+ if (argc != optind + 2) {
+ help("psr-mba-set");
+ return 2;
+ }
+
+ domid = find_domain(argv[optind]);
+ thrtl = strtoll(argv[optind + 1], NULL , 0);
+
+ ret = libxl_psr_set_val(ctx, domid, type, &target_map, thrtl);
+
+ libxl_bitmap_dispose(&target_map);
+ return ret;
+}
+
static int psr_mba_hwinfo(void)
{
int rc;
--
1.9.1
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v3 15/15] docs: add MBA description in docs
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (13 preceding siblings ...)
2017-09-05 9:32 ` [PATCH v3 14/15] tools: implement new generic set value interface and MBA set " Yi Sun
@ 2017-09-05 9:32 ` Yi Sun
2017-09-19 11:37 ` Roger Pau Monné
14 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-05 9:32 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng, dgdegra,
roger.pau
This patch adds MBA description in related documents.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
---
v2:
- state the value type shown by 'psr-mba-show'. For linear mode,
it shows decimal value. For non-linear mode, it shows hexadecimal
value.
(suggested by Chao Peng)
---
docs/man/xl.pod.1.in | 34 +++++++++++++++++++++++++
docs/misc/xl-psr.markdown | 63 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+)
diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 16c8306..e644b19 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1798,6 +1798,40 @@ processed.
=back
+=head2 Memory Bandwidth Allocation
+
+Intel Skylake and later server platforms offer capabilities to configure and
+make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
+OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
+control system via exposing control over a credit-based throttling mechanism.
+In the Xen implementation, MBA is used to control memory bandwidth on VM basis.
+To enforce bandwidth on a specific domain, just set throttling value (THRTL)
+for the domain.
+
+=over 4
+
+=item B<psr-mba-set> [I<OPTIONS>] I<domain-id> I<thrtl>
+
+Set throttling value (THRTL) for a domain. For how to specify I<thrtl>
+please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-s SOCKET>, B<--socket=SOCKET>
+
+Specify the socket to process, otherwise all sockets are processed.
+
+=back
+
+=item B<psr-mba-show> [I<domain-id>]
+
+Show MBA settings for a certain domain or all domains. For linear mode, it
+shows the decimal value. For non-linear mode, it shows hexadecimal value.
+
+=back
+
=head1 IGNORED FOR COMPATIBILITY WITH XM
xl is mostly command-line compatible with the old xm utility used with
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index 04dd957..39fc801 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -186,6 +186,69 @@ Setting data CBM for a domain:
Setting the same code and data CBM for a domain:
`xl psr-cat-set <domid> <cbm>`
+## Memory Bandwidth Allocation (MBA)
+
+Memory Bandwidth Allocation (MBA) is a new feature available on Intel
+Skylake and later server platforms that allows an OS or Hypervisor/VMM to
+slow misbehaving apps/VMs or create advanced closed-loop control system via
+exposing control over a credit-based throttling mechanism. To enforce bandwidth
+on a specific domain, just set throttling value (THRTL) into Class of Service
+(COS). MBA provides two THRTL mode. One is linear mode and the other is
+non-linear mode.
+
+In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
+not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
+to 10% delay applied).
+
+If linear values are not supported then input delay values are powers-of-two
+from zero to the THRTL_MAX value from CPUID. In this case any values not a power
+of two will be rounded down the next nearest power of two.
+
+For example, assuming a system with 2 domains:
+
+ * A THRTL of 0x0 for every domain means each domain can access the whole cache
+ without any delay. This is the default.
+
+ * Linear mode: Giving one domain a THRTL of 0xC and the other domain's 0 means
+ that the first domain gets 10% delay to access the cache and the other one
+ without any delay.
+
+ * Non-linear mode: Giving one domain a THRTL of 0xC and the other domain's 0
+ means that the first domain gets 8% delay to access the cache and the other
+ one without any delay.
+
+For more detailed information please refer to Intel SDM chapter
+"Introduction to Memory Bandwidth Allocation".
+
+In Xen's implementation, THRTL can be configured with libxl/xl interfaces but
+COS is maintained in hypervisor only. The cache partition granularity is per
+domain, each domain has COS=0 assigned by default, the corresponding THRTL is
+0, which means all the cache resource can be accessed without delay.
+
+### xl interfaces
+
+System MBA information such as maximum COS and maximum THRTL can be obtained by:
+
+`xl psr-hwinfo --mba`
+
+The simplest way to change a domain's THRTL from its default is running:
+
+`xl psr-mba-set [OPTIONS] <domid> <thrtl>`
+
+In a multi-socket system, the same thrtl will be set on each socket by default.
+Per socket thrtl can be specified with the `--socket SOCKET` option.
+
+Setting the THRTL may not be successful if insufficient COS is available. In
+such case unused COS(es) may be freed by setting THRTL of all related domains to
+its default value(0).
+
+Per domain THRTL settings can be shown by:
+
+`xl psr-mba-show [OPTIONS] <domid>`
+
+For linear mode, it shows the decimal value. For non-linear mode, it shows
+hexadecimal value.
+
## Reference
[1] Intel SDM
--
1.9.1
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^ permalink raw reply related [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-05 9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
@ 2017-09-18 17:16 ` Roger Pau Monné
2017-09-19 6:07 ` Jan Beulich
2017-09-20 3:06 ` Yi Sun
0 siblings, 2 replies; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-18 17:16 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote:
> +* xl interfaces:
> +
> + 1. `psr-mba-show [domain-id]`:
Is this limited to domain-id, or one can also use the domain name?
Most of the xl commands accept either a domain-id or a domain-name.
> +
> + Show memory bandwidth throttling for domain. Under different modes, it
> + shows different type of data.
> +
> + There are two modes:
> + Linear mode: the response of throttling value is linear.
> + Non-linear mode: the response of throttling value is non-linear.
> +
> + For linear mode, it shows the decimal value. For non-linear mode, it shows
> + hexadecimal value.
> +
> + 2. `psr-mba-set [OPTIONS] <domain-id> <throttling>`:
> +
> + Set memory bandwidth throttling for domain.
> +
> + Options:
> + '-s': Specify the socket to process, otherwise all sockets are processed.
> +
> + Throttling value set in register implies the approximate amount of delaying
> + the traffic between core and memory. The higher throttling value results in
> + lower bandwidth. The max throttling value (MBA_MAX) supported can be got
s/got/obtained/
> + through CPUID.
How can one get this value empirically? Do I need to use a external
tool?
> +
> + Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
> + if the MBA_MAX value is 90, the input precision is 10%. Values not an even
> + multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
> + delay applied) by HW automatically.
> +
> + Non-linear mode: input delay values are powers-of-two from zero to the
> + MBA_MAX value from CPUID. In this case any values not a power of two will
> + be rounded down the next nearest power of two by HW automatically.
Both of the above descriptions should be moved to mba-show IMHO, the
description there is incomplete and not helpful.
> +
> +# Technical details
> +
> +MBA is a member of Intel PSR features, it shares the base PSR infrastructure
> +in Xen.
> +
> +## Hardware perspective
> +
> + MBA defines a range of MSRs to support specifying a delay value (Thrtl) per
> + COS, with details below.
> +
> + ```
> + +----------------------------+----------------+
> + | MSR (per socket) | Address |
> + +----------------------------+----------------+
> + | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
> + +----------------------------+----------------+
> + | ... | ... |
> + +----------------------------+----------------+
> + | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n |
> + +----------------------------+----------------+
> + ```
> +
> + When context switch happens, the COS ID of domain is written to per-thread MSR
> + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation according
I think this is missing some context of the relation between a thread
and the MSR. I assume it's related to IA32_PQR_ASSOC, but I have no
idea what that constant means.
What's more, Xen doesn't have threads, so you should maybe speak about
vCPUs instead?
> + to the throttling value stored in the Thrtl MSR register.
> +
> +## The relationship between MBA and CAT/CDP
> +
> + Generally speaking, MBA is completely independent of CAT/CDP, and any
> + combination may be applied at any time, e.g. enabling MBA with CAT
> + disabled.
> +
> + But it needs to be noticed that MBA shares COS infrastructure with CAT,
> + although MBA is enumerated by different CPUID leaf from CAT (which
> + indicates that the max COS of MBA may be different from CAT). In some
> + cases, a domain is permitted to have a COS that is beyond one (or more)
> + of PSR features but within the others. For instance, let's assume the max
> + COS of MBA is 8 but the max COS of L3 CAT is 16, when a domain is assigned
> + 9 as COS, the L3 CAT CBM associated to COS 9 would be enforced, but for MBA,
> + the HW works as default value is set since COS 9 is beyond the max COS (8)
> + of MBA.
> +
> +## Design Overview
> +
> +* Core COS/Thrtl association
> +
> + When enforcing Memory Bandwidth Allocation, all cores of domains have
> + the same default Thrtl MSR (COS0) which stores the same Thrtl (0). The
> + default Thrtl MSR is used only in hypervisor and is transparent to tool stack
> + and user.
> +
> + System administrators can change PSR allocation policy at runtime by
> + using the tool stack. Since MBA shares COS ID with CAT/CDP, a COS ID
> + corresponds to a 2-tuple, like [CBM, Thrtl] with only-CAT enabled, when CDP
> + is enabled, the COS ID corresponds to a 3-tuple, like [Code_CBM, Data_CBM,
> + Thrtl]. If neither CAT nor CDP is enabled, things are easier, since one COS
> + ID corresponds to one Thrtl.
> +
> +* VCPU schedule
> +
> + This part reuses CAT COS infrastructure.
> +
> +* Multi-sockets
> +
> + Different sockets may have different MBA ability (like max COS)
> + although it is consistent on the same socket. So the capability
> + of per-socket MBA is specified.
> +
> + This part reuses CAT COS infrastructure.
> +
> +## Implementation Description
> +
> +* Hypervisor interfaces:
> +
> + 1. Boot line param: "psr=mba" to enable the feature.
> +
> + 2. SYSCTL:
> + - XEN_SYSCTL_PSR_MBA_get_info: Get system MBA information.
So this is likely how one gets the mentioned MBA_MAX?
> +
> + 3. DOMCTL:
> + - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get throttling for a domain.
> + - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set throttling for a domain.
> +
> +* xl interfaces:
> +
> + 1. psr-mba-show [domain-id]
> + Show system/domain runtime MBA throttling value. For linear mode,
> + it shows the decimal value. For non-linear mode, it shows hexadecimal
> + value.
> + => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
> +
> + 2. psr-mba-set [OPTIONS] <domain-id> <throttling>
> + Set bandwidth throttling for a domain.
> + => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
> +
> + 3. psr-hwinfo
> + Show PSR HW information, including L3 CAT/CDP/L2 CAT/MBA.
> + => XEN_SYSCTL_PSR_MBA_get_info
'psr-hwinfo' seems to be completely missing from the 'xl interfaces:'
section above.
> +* Key data structure:
> +
> + 1. Feature HW info
> +
> + ```
> + struct {
> + unsigned int thrtl_max;
> + bool linear;
> + } mba;
> +
> + - Member `thrtl_max`
> +
> + `thrtl_max` is the max throttling value to be set, i.e. MBA_MAX.
> +
> + - Member `linear`
> +
> + `linear` means the response of delay value is linear or not.
> +
> + As mentioned above, MBA is a member of Intel PSR features, it would
> + share the base PSR infrastructure in Xen. For example, the 'cos_max'
> + is a common HW property for all features. So, for other data structure
> + details, please refer 'intel_psr_cat_cdp.pandoc'.
^ to
> +
> +# Limitations
> +
> +MBA can only work on HW which enables it (check by CPUID).
^ s/enables/supports/.
> +
> +# Testing
> +
> +We can execute these commands to verify MBA on different HWs supporting them.
> +
> +For example:
> + 1. User can get the MBA hardware info through 'psr-hwinfo' command. From
> + result, user can know if this hardware works under linear mode or non-
> + linear mode, the max throttling value (MBA_MAX) and so on.
> +
> + root@:~$ xl psr-hwinfo --mba
> + Memory Bandwidth Allocation (MBA):
> + Socket ID : 0
> + Linear Mode : Enabled
> + Maximum COS : 7
> + Maximum Throttling Value: 90
> + Default Throttling Value: 0
> +
> + 2. Then, user can set a throttling value to a domain. For example, set '0xa',
> + i.e 10% delay.
> +
> + root@:~$ xl psr-mba-set 1 0xa
> +
> + 3. User can check the current configuration of the domain through
> + 'psr-mab-show'. For linear mode, the decimal value is shown.
> +
> + root@:~$ xl psr-mba-show 1
> + Socket ID : 0
> + Default THRTL : 0
> + ID NAME THRTL
> + 1 ubuntu14 10
The example seems better now IMHO.
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-18 17:16 ` Roger Pau Monné
@ 2017-09-19 6:07 ` Jan Beulich
2017-09-20 2:59 ` Yi Sun
2017-09-20 3:06 ` Yi Sun
1 sibling, 1 reply; 62+ messages in thread
From: Jan Beulich @ 2017-09-19 6:07 UTC (permalink / raw)
To: roger.pau
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
yi.y.sun, julien.grall, mengxu, xen-devel, chao.p.peng, dgdegra
>>> Roger Pau Monné <roger.pau@citrix.com> 09/18/17 7:21 PM >>>
>On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote:
>> +## Hardware perspective
>> +
>> + MBA defines a range of MSRs to support specifying a delay value (Thrtl) per
>> + COS, with details below.
>> +
>> + ```
>> + +----------------------------+----------------+
>> + | MSR (per socket) | Address |
>> + +----------------------------+----------------+
>> + | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
>> + +----------------------------+----------------+
>> + | ... | ... |
>> + +----------------------------+----------------+
>> + | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n |
>> + +----------------------------+----------------+
>> + ```
>> +
>> + When context switch happens, the COS ID of domain is written to per-thread MSR
>> + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation according
>
>I think this is missing some context of the relation between a thread
>and the MSR. I assume it's related to IA32_PQR_ASSOC, but I have no
>idea what that constant means.
>
>What's more, Xen doesn't have threads, so you should maybe speak about
>vCPUs instead?
I think talk is of hardware aspects here, i.e. "thread" as in "hyper-thread".
Jan
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-09-05 9:32 ` [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
@ 2017-09-19 8:03 ` Roger Pau Monné
2017-09-20 3:12 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 8:03 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:24PM +0800, Yi Sun wrote:
> diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
> index 0669c31..a953157 100644
> --- a/xen/include/public/domctl.h
> +++ b/xen/include/public/domctl.h
> @@ -37,7 +37,7 @@
> #include "hvm/save.h"
> #include "memory.h"
>
> -#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000e
> +#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000f
>
> /*
> * NB. xen_domctl.domain is an IN/OUT parameter for this operation.
> @@ -1135,21 +1135,21 @@ struct xen_domctl_monitor_op {
> typedef struct xen_domctl_monitor_op xen_domctl_monitor_op_t;
> DEFINE_XEN_GUEST_HANDLE(xen_domctl_monitor_op_t);
>
> -struct xen_domctl_psr_cat_op {
> -#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM 0
> -#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM 1
> -#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE 2
> -#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA 3
> -#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE 4
> -#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
> -#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
> -#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
> +struct xen_domctl_psr_alloc {
> +#define XEN_DOMCTL_PSR_ALLOC_SET_L3_CBM 0
> +#define XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM 1
> +#define XEN_DOMCTL_PSR_ALLOC_SET_L3_CODE 2
> +#define XEN_DOMCTL_PSR_ALLOC_SET_L3_DATA 3
> +#define XEN_DOMCTL_PSR_ALLOC_GET_L3_CODE 4
> +#define XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA 5
> +#define XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM 6
> +#define XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM 7
IMHO, the _ALLOC_ part is not needed here, ALLOC_GET/SET seems quite
weird to me, and redundant, since the type itself already contains
_alloc).
> uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
This comments needs fixing.
> uint32_t target; /* IN */
> uint64_t data; /* IN/OUT */
> };
> -typedef struct xen_domctl_psr_cat_op xen_domctl_psr_cat_op_t;
> -DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_cat_op_t);
> +typedef struct xen_domctl_psr_alloc xen_domctl_psr_alloc_t;
> +DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_alloc_t);
>
> struct xen_domctl {
> uint32_t cmd;
> @@ -1226,7 +1226,7 @@ struct xen_domctl {
> #define XEN_DOMCTL_setvnumainfo 74
> #define XEN_DOMCTL_psr_cmt_op 75
> #define XEN_DOMCTL_monitor_op 77
> -#define XEN_DOMCTL_psr_cat_op 78
> +#define XEN_DOMCTL_psr_alloc 78
> #define XEN_DOMCTL_soft_reset 79
> #define XEN_DOMCTL_gdbsx_guestmemio 1000
> #define XEN_DOMCTL_gdbsx_pausevcpu 1001
> @@ -1289,7 +1289,7 @@ struct xen_domctl {
> struct xen_domctl_vnuma vnuma;
> struct xen_domctl_psr_cmt_op psr_cmt_op;
> struct xen_domctl_monitor_op monitor_op;
> - struct xen_domctl_psr_cat_op psr_cat_op;
> + struct xen_domctl_psr_alloc psr_alloc;
> uint8_t pad[128];
> } u;
> };
> diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
> index 9e51af6..4759b10 100644
> --- a/xen/include/public/sysctl.h
> +++ b/xen/include/public/sysctl.h
> @@ -36,7 +36,7 @@
> #include "physdev.h"
> #include "tmem.h"
>
> -#define XEN_SYSCTL_INTERFACE_VERSION 0x0000000F
> +#define XEN_SYSCTL_INTERFACE_VERSION 0x00000010
>
> /*
> * Read console content from Xen buffer ring.
> @@ -743,22 +743,22 @@ struct xen_sysctl_pcitopoinfo {
> typedef struct xen_sysctl_pcitopoinfo xen_sysctl_pcitopoinfo_t;
> DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
>
> -#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
> -#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
> -struct xen_sysctl_psr_cat_op {
> +#define XEN_SYSCTL_PSR_ALLOC_get_l3_info 0
> +#define XEN_SYSCTL_PSR_ALLOC_get_l2_info 1
Same here, I would drop the _ALLOC_.
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general
2017-09-05 9:32 ` [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
@ 2017-09-19 8:22 ` Roger Pau Monné
0 siblings, 0 replies; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 8:22 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:25PM +0800, Yi Sun wrote:
> This patch renames 'cbm_type' to 'psr_type' to make it be general.
s/make it be general/generalize it/.
> Then, we can reuse this for all psr allocation features.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA
2017-09-05 9:32 ` [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA Yi Sun
@ 2017-09-19 8:55 ` Roger Pau Monné
2017-09-20 3:22 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 8:55 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:26PM +0800, Yi Sun wrote:
> This patch implements main data structures of MBA.
>
> Like CAT features, MBA HW info has cos_max which means the max thrtl
> register number, and thrtl_max which means the max throttle value
> (delay value). It also has a flag to represent if the throttle
> value is linear or not.
>
> One thrtl register of MBA stores a throttle value for one or more
> domains. The throttle value means the transaction time between L2
> cache and next level memory to be delayed.
"The throttle value contains the delay between L2 cache and the next
cache level."
Seems better, but I'm not a native speaker anyway.
>
> This patch also implements init flow for MBA and register stub
> callback functions.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - replace 'psr_val_type' to 'psr_type'. Also, change 'PSR_VAL_TYPE_MBA' to
> 'PSR_TYPE_MBA_THRTL'.
> (suggested by Roger Pau Monné)
> - replace 'MBA_LINEAR' to 'MBA_LINEAR_MASK' to make the name more clear.
> (suggested by Roger Pau Monné)
> - replase 'cat_info'/'mba_info' to 'cat'/'mba' to make the names shorter.
> (suggested by Roger Pau Monné)
> - change type of 'linear' to 'bool'.
> (suggested by Roger Pau Monné)
> - make format string of printf in one line.
> (suggested by Roger Pau Monné)
> v2:
> - modify commit message to replace 'cos register' to 'thrtl register' to
> make it accurate.
> (suggested by Chao Peng)
> - restore the place of the sentence to assign value to 'feat->cbm_len'
> because the MBA init flow is splitted out as a separate function in v1.
> (suggested by Chao Peng)
> - add comment to explain what the MBA thrtl defaul value '0' stands for.
> (suggested by Chao Peng)
> - check 'thrtl_max' under linear mode. It could not be euqal or larger than
> 100.
> (suggested by Chao Peng)
> v1:
> - rebase codes onto L2 CAT v15.
> - move comment to appropriate place.
> (suggested by Chao Peng)
> - implement 'mba_init_feature' and keep 'cat_init_feature'.
> (suggested by Chao Peng)
> - keep 'regs.b' into a local variable to avoid reading CPUID every time.
> (suggested by Chao Peng)
> ---
> xen/arch/x86/psr.c | 140 ++++++++++++++++++++++++++++++++++------
> xen/include/asm-x86/msr-index.h | 1 +
> xen/include/asm-x86/psr.h | 2 +
> 3 files changed, 125 insertions(+), 18 deletions(-)
>
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index 4166a1c..10776d2 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -27,13 +27,16 @@
> * - CMT Cache Monitoring Technology
> * - COS/CLOS Class of Service. Also mean COS registers.
> * - COS_MAX Max number of COS for the feature (minus 1)
> + * - MBA Memory Bandwidth Allocation
> * - MSRs Machine Specific Registers
> * - PSR Intel Platform Shared Resource
> + * - THRTL_MAX Max throttle value (delay value) of MBA
> */
>
> #define PSR_CMT (1u << 0)
> #define PSR_CAT (1u << 1)
> #define PSR_CDP (1u << 2)
> +#define PSR_MBA (1u << 3)
>
> #define CAT_CBM_LEN_MASK 0x1f
> #define CAT_COS_MAX_MASK 0xffff
> @@ -60,10 +63,14 @@
> */
> #define MAX_COS_NUM 2
>
> +#define MBA_LINEAR_MASK (1u << 2)
> +#define MBA_THRTL_MAX_MASK 0xfff
> +
> enum psr_feat_type {
> FEAT_TYPE_L3_CAT,
> FEAT_TYPE_L3_CDP,
> FEAT_TYPE_L2_CAT,
> + FEAT_TYPE_MBA,
> FEAT_TYPE_NUM,
> FEAT_TYPE_UNKNOWN,
> };
> @@ -71,7 +78,6 @@ enum psr_feat_type {
> /*
> * This structure represents one feature.
> * cos_max - The max COS registers number got through CPUID.
> - * cbm_len - The length of CBM got through CPUID.
> * cos_reg_val - Array to store the values of COS registers. One entry stores
> * the value of one COS register.
> * For L3 CAT and L2 CAT, one entry corresponds to one COS_ID.
> @@ -80,9 +86,23 @@ enum psr_feat_type {
> * cos_reg_val[1] (Code).
> */
> struct feat_node {
> - /* cos_max and cbm_len are common values for all features so far. */
> + /* cos_max is common values for all features so far. */
...common among all features...
> unsigned int cos_max;
> - unsigned int cbm_len;
> +
> + /* Feature specific HW info. */
> + union {
> + struct {
> + /* The length of CBM got through CPUID. */
> + unsigned int cbm_len;
> + } cat;
> +
> + struct {
> + /* The max throttling value got through CPUID. */
> + unsigned int thrtl_max;
> + bool linear;
> + } mba;
> + };
> +
> uint32_t cos_reg_val[MAX_COS_REG_CNT];
> };
>
> @@ -161,6 +181,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
> */
> static struct feat_node *feat_l3;
> static struct feat_node *feat_l2_cat;
> +static struct feat_node *feat_mba;
>
> /* Common functions */
> #define cat_default_val(len) (0xffffffff >> (32 - (len)))
> @@ -272,7 +293,7 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
> return true;
> }
>
> -/* CAT common functions implementation. */
> +/* Implementation of allocation features' functions. */
> static int cat_init_feature(const struct cpuid_leaf *regs,
> struct feat_node *feat,
> struct psr_socket_info *info,
> @@ -288,8 +309,8 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
> if ( !regs->a || !regs->d )
> return -ENOENT;
>
> - feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
> feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
> + feat->cat.cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
>
> switch ( type )
> {
> @@ -299,12 +320,12 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
> return -ENOENT;
>
> /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
> - feat->cos_reg_val[0] = cat_default_val(feat->cbm_len);
> + feat->cos_reg_val[0] = cat_default_val(feat->cat.cbm_len);
>
> wrmsrl((type == FEAT_TYPE_L3_CAT ?
> MSR_IA32_PSR_L3_MASK(0) :
> MSR_IA32_PSR_L2_MASK(0)),
> - cat_default_val(feat->cbm_len));
> + cat_default_val(feat->cat.cbm_len));
>
> break;
>
> @@ -319,11 +340,13 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
> feat->cos_max = (feat->cos_max - 1) >> 1;
>
> /* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
> - get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len);
> - get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len);
> + get_cdp_code(feat, 0) = cat_default_val(feat->cat.cbm_len);
> + get_cdp_data(feat, 0) = cat_default_val(feat->cat.cbm_len);
>
> - wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len));
> - wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len));
> + wrmsrl(MSR_IA32_PSR_L3_MASK(0),
> + cat_default_val(feat->cat.cbm_len));
> + wrmsrl(MSR_IA32_PSR_L3_MASK(1),
> + cat_default_val(feat->cat.cbm_len));
> rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
> wrmsrl(MSR_IA32_PSR_L3_QOS_CFG,
> val | (1ull << PSR_L3_QOS_CDP_ENABLE_BIT));
> @@ -343,7 +366,50 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
>
> printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
> cat_feat_name[type], cpu_to_socket(smp_processor_id()),
> - feat->cos_max, feat->cbm_len);
> + feat->cos_max, feat->cat.cbm_len);
> +
> + return 0;
> +}
> +
> +static int mba_init_feature(const struct cpuid_leaf *regs,
> + struct feat_node *feat,
> + struct psr_socket_info *info,
> + enum psr_feat_type type)
> +{
> + /* No valid value so do not enable feature. */
> + if ( !regs->a || !regs->d )
> + return -ENOENT;
> +
> + if ( type != FEAT_TYPE_MBA )
> + return -ENOENT;
You can join the two checks above in a single if.
> +
> + feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
> + if ( feat->cos_max < 1 )
> + return -ENOENT;
> +
> + feat->mba.thrtl_max = (regs->a & MBA_THRTL_MAX_MASK) + 1;
> +
> + if ( regs->c & MBA_LINEAR_MASK )
> + {
> + feat->mba.linear = true;
> +
> + if ( feat->mba.thrtl_max >= 100 )
> + return -ENOENT;
> + }
> +
> + /* We reserve cos=0 as default thrtl (0) which means no delay. */
> + feat->cos_reg_val[0] = 0;
AFAICT feat is allocated using xzalloc, so this will already be 0.
> + wrmsrl(MSR_IA32_PSR_MBA_MASK(0), 0);
> +
> + /* Add this feature into array. */
> + info->features[type] = feat;
> +
> + if ( !opt_cpu_info )
> + return 0;
> +
> + printk(XENLOG_INFO "MBA: enabled on socket %u, cos_max:%u, thrtl_max:%u, linear:%u.\n",
> + cpu_to_socket(smp_processor_id()),
> + feat->cos_max, feat->mba.thrtl_max, feat->mba.linear);
>
> return 0;
> }
> @@ -355,7 +421,7 @@ static bool cat_get_feat_info(const struct feat_node *feat,
> return false;
>
> data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
> - data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cbm_len;
> + data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cat.cbm_len;
> data[PSR_INFO_IDX_CAT_FLAG] = 0;
>
> return true;
> @@ -421,6 +487,26 @@ static const struct feat_props l2_cat_props = {
> .write_msr = l2_cat_write_msr,
> };
>
> +/* MBA props */
> +static bool mba_get_feat_info(const struct feat_node *feat,
> + uint32_t data[], unsigned int array_len)
> +{
> + return false;
> +}
> +
> +static void mba_write_msr(unsigned int cos, uint32_t val,
> + enum psr_type type)
> +{
> +}
> +
> +static const struct feat_props mba_props = {
> + .cos_num = 1,
> + .type[0] = PSR_TYPE_MBA_THRTL,
> + .alt_type = PSR_TYPE_UNKNOWN,
> + .get_feat_info = mba_get_feat_info,
> + .write_msr = mba_write_msr,
> +};
> +
> static void __init parse_psr_bool(char *s, char *value, char *feature,
> unsigned int mask)
> {
> @@ -456,6 +542,7 @@ static void __init parse_psr_param(char *s)
> parse_psr_bool(s, val_str, "cmt", PSR_CMT);
> parse_psr_bool(s, val_str, "cat", PSR_CAT);
> parse_psr_bool(s, val_str, "cdp", PSR_CDP);
> + parse_psr_bool(s, val_str, "mba", PSR_MBA);
>
> if ( val_str && !strcmp(s, "rmid_max") )
> opt_rmid_max = simple_strtoul(val_str, NULL, 0);
> @@ -862,7 +949,7 @@ static int insert_val_into_array(uint32_t val[],
> if ( array_len < props->cos_num )
> return -ENOSPC;
>
> - if ( !psr_check_cbm(feat->cbm_len, new_val) )
> + if ( !psr_check_cbm(feat->cat.cbm_len, new_val) )
> return -EINVAL;
>
> /*
> @@ -1380,6 +1467,10 @@ static int psr_cpu_prepare(void)
> (feat_l2_cat = xzalloc(struct feat_node)) == NULL )
> return -ENOMEM;
>
> + if ( feat_mba == NULL &&
> + (feat_mba = xzalloc(struct feat_node)) == NULL )
> + return -ENOMEM;
> +
> return 0;
> }
>
> @@ -1389,6 +1480,7 @@ static void psr_cpu_init(void)
> unsigned int socket, cpu = smp_processor_id();
> struct feat_node *feat;
> struct cpuid_leaf regs;
> + uint32_t reg_b;
Not sure of the benefit between using regs.b or reg_b (it's only 1
char shorter).
>
> if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) )
> goto assoc_init;
> @@ -1407,7 +1499,8 @@ static void psr_cpu_init(void)
> spin_lock_init(&info->ref_lock);
>
> cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
> - if ( regs.b & PSR_RESOURCE_TYPE_L3 )
> + reg_b = regs.b;
> + if ( reg_b & PSR_RESOURCE_TYPE_L3 )
> {
> cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s);
>
> @@ -1428,8 +1521,7 @@ static void psr_cpu_init(void)
> }
> }
>
> - cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
> - if ( regs.b & PSR_RESOURCE_TYPE_L2 )
> + if ( reg_b & PSR_RESOURCE_TYPE_L2 )
> {
> cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);
>
> @@ -1441,6 +1533,18 @@ static void psr_cpu_init(void)
> feat_l2_cat = feat;
> }
>
> + if ( reg_b & PSR_RESOURCE_TYPE_MBA )
> + {
> + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, ®s);
> +
> + feat = feat_mba;
> + feat_mba = NULL;
> + if ( !mba_init_feature(®s, feat, info, FEAT_TYPE_MBA) )
Seems kind of pointless that mba_init_feature returns an error code
when it's ignored by it's callers. You could switch it to bool if you
are going to use it like that.
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/15] x86: implement get hw info flow for MBA
2017-09-05 9:32 ` [PATCH v3 05/15] x86: implement get hw info " Yi Sun
@ 2017-09-19 9:08 ` Roger Pau Monné
2017-09-20 5:05 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 9:08 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:27PM +0800, Yi Sun wrote:
> This patch implements get HW info flow for MBA including its callback
> function and sysctl interface.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - replace 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
> (suggested by Roger Pau Monné)
> v2:
> - use 'XEN_SYSCTL_PSR_MBA_LINEAR' to set MBA feature HW info.
> (suggested by Chao Peng)
> v1:
> - sort 'PSR_INFO_IDX_' macros as feature.
> (suggested by Chao Peng)
> - rename 'PSR_INFO_IDX_MBA_LINEAR' to 'PSR_INFO_IDX_MBA_FLAG'.
> - rename 'linear' in 'struct mba_info' to 'flags' for future extension.
> (suggested by Chao Peng)
> ---
> xen/arch/x86/psr.c | 17 ++++++++++++++++-
> xen/arch/x86/sysctl.c | 19 +++++++++++++++++++
> xen/include/asm-x86/psr.h | 2 ++
> xen/include/public/sysctl.h | 8 ++++++++
> 4 files changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index 10776d2..0486d2d 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -263,6 +263,10 @@ static enum psr_feat_type psr_type_to_feat_type(enum psr_type type)
> feat_type = FEAT_TYPE_L2_CAT;
> break;
>
> + case PSR_TYPE_MBA_THRTL:
> + feat_type = FEAT_TYPE_MBA;
> + break;
> +
> default:
> ASSERT_UNREACHABLE();
> }
> @@ -491,7 +495,18 @@ static const struct feat_props l2_cat_props = {
> static bool mba_get_feat_info(const struct feat_node *feat,
> uint32_t data[], unsigned int array_len)
> {
> - return false;
> + if ( array_len != PSR_INFO_ARRAY_SIZE )
> + return false;
> +
> + data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
> + data[PSR_INFO_IDX_MBA_THRTL_MAX] = feat->mba.thrtl_max;
> +
> + if ( feat->mba.linear )
> + data[PSR_INFO_IDX_MBA_FLAG] |= XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
> + else
> + data[PSR_INFO_IDX_MBA_FLAG] &= ~XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
This branch of the if shouldn't be needed...
> +
> + return true;
> }
>
> static void mba_write_msr(unsigned int cos, uint32_t val,
> diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
> index 1d3dbd0..4634cad 100644
> --- a/xen/arch/x86/sysctl.c
> +++ b/xen/arch/x86/sysctl.c
> @@ -214,6 +214,25 @@ long arch_do_sysctl(
> break;
> }
>
> + case XEN_SYSCTL_PSR_ALLOC_get_mba_info:
> + {
> + ret = psr_get_info(sysctl->u.psr_alloc.target,
> + PSR_TYPE_MBA_THRTL, data, ARRAY_SIZE(data));
... because data should be initialized, ie:
uint32_t data[PSR_INFO_ARRAY_SIZE] = { 0 };
So that we don't leak stack data in the sysctl.
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 06/15] x86: implement get value interface for MBA
2017-09-05 9:32 ` [PATCH v3 06/15] x86: implement get value interface " Yi Sun
@ 2017-09-19 9:15 ` Roger Pau Monné
2017-09-20 5:09 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 9:15 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:28PM +0800, Yi Sun wrote:
> This patch implements get value domctl interface for MBA.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
> ---
> v3:
> - change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
> (suggested by Roger Pau Monné)
> ---
> xen/arch/x86/domctl.c | 7 +++++++
> xen/include/public/domctl.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
> index 696eff2..7902af7 100644
> --- a/xen/arch/x86/domctl.c
> +++ b/xen/arch/x86/domctl.c
> @@ -1496,6 +1496,13 @@ long arch_do_domctl(
> copyback = true;
> break;
>
> + case XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL:
> + ret = psr_get_val(d, domctl->u.psr_alloc.target,
> + &val32, PSR_TYPE_MBA_THRTL);
> + domctl->u.psr_alloc.data = val32;
Hm, why does psr_get_val take a uint32_t * instead of a uint64_t *? So
that you can directly pass &domctl->u.psr_alloc.data.
Or the other way around, why is domctl->u.psr_alloc.data a uint64_t
instead of a uint32_t?
Thanks, Roger.
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https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 07/15] x86: implement set value flow for MBA
2017-09-05 9:32 ` [PATCH v3 07/15] x86: implement set value flow " Yi Sun
@ 2017-09-19 9:57 ` Roger Pau Monné
2017-09-20 5:39 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 9:57 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:29PM +0800, Yi Sun wrote:
> This patch implements set value flow for MBA including its callback
> function and domctl interface.
>
> It also changes the memebers in 'cos_write_info' to transfer the
> feature array, feature properties array and value array. Then, we
> can write all features values on the cos id into MSRs.
>
> Because multiple features may co-exist, we need handle all features to write
> values of them into a COS register with new COS ID. E.g:
> 1. L3 CAT and MBA co-exist.
> 2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of Dom1 is 0x1ff,
> the MBA Thrtle of Dom1 is 0xa.
> 3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because COS ID 2 is
> used by Dom2 too, we have to pick a new COS ID 3. The values of Dom1 on
> COS ID 3 are all default values as below:
> ---------
> | COS 3 |
> ---------
> L3 CAT | 0x7ff |
> ---------
> MBA | 0x0 |
> ---------
> 4. After setting, the L3 CAT CBM value of Dom1 should be kept and the new MBA
> Thrtl is set. So, the values on COS ID 3 should be below.
> ---------
> | COS 3 |
> ---------
> L3 CAT | 0x1ff |
> ---------
> MBA | 0x14 |
> ---------
>
> So, we should write all features values into their MSRs. That requires the
> feature array, feature properties array and value array are input.
^ as
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - modify commit message to make it clear.
> (suggested by Roger Pau Monné)
> - modify functionality of 'check_val' to make it simple to only check value.
> Change the last parameter type from 'unsigned long *' to 'unsigned long'.
> (suggested by Roger Pau Monné)
> - call rdmsrl to get value just written into MSR for MBA. Because HW can
> automatically change input value to what it wants.
> (suggested by Roger Pau Monné)
> - change type of 'write_msr' to 'uint32_t' to return the value actually
> written into MSR. Then, change 'do_write_psr_msrs' to set the returned
> value into 'cos_reg_val[]'
> - move the declaration of 'j' into loop in 'do_write_psr_msrs'.
> (suggested by Roger Pau Monné)
> - change 'mba_info' to 'mba'.
> (suggested by Roger Pau Monné)
> - change 'cat_info' to 'cat'.
> (suggested by Roger Pau Monné)
> - rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
> from name.
> (suggested by Roger Pau Monné)
> - change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
> (suggested by Roger Pau Monné)
> v2:
> - remove linear mode 'thrtl_max' check in 'mba_check_thrtl' because it has
> been checked in 'mba_init_feature'.
> (suggested by Chao Peng)
> - for non-linear mode, check if '*thrtl' is not 0 in 'mba_check_thrtl'. If
> it is 0, we do not need to change it.
> (suggested by Chao Peng)
> - move comments to explain changes of 'cos_write_info' from psr.c to commit
> message.
> (suggested by Chao Peng)
> ---
> xen/arch/x86/domctl.c | 6 ++
> xen/arch/x86/psr.c | 146 +++++++++++++++++++++++++++-----------------
> xen/include/public/domctl.h | 1 +
> 3 files changed, 96 insertions(+), 57 deletions(-)
>
> diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
> index 7902af7..8550d06 100644
> --- a/xen/arch/x86/domctl.c
> +++ b/xen/arch/x86/domctl.c
> @@ -1468,6 +1468,12 @@ long arch_do_domctl(
> PSR_TYPE_L2_CBM);
> break;
>
> + case XEN_DOMCTL_PSR_ALLOC_SET_MBA_THRTL:
> + ret = psr_set_val(d, domctl->u.psr_alloc.target,
> + domctl->u.psr_alloc.data,
> + PSR_TYPE_MBA_THRTL);
> + break;
> +
> case XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM:
> ret = psr_get_val(d, domctl->u.psr_alloc.target,
> &val32, PSR_TYPE_L3_CBM);
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index 0486d2d..d633194 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -137,7 +137,10 @@ static const struct feat_props {
> uint32_t data[], unsigned int array_len);
>
> /* write_msr is used to write out feature MSR register. */
> - void (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type);
> + uint32_t (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type);
> +
> + /* check_val is used to check if input val fulfills SDM requirement. */
> + bool (*check_val)(const struct feat_node *feat, unsigned long val);
> } *feat_props[FEAT_TYPE_NUM];
>
> /*
> @@ -274,29 +277,6 @@ static enum psr_feat_type psr_type_to_feat_type(enum psr_type type)
> return feat_type;
> }
>
> -static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
> -{
> - unsigned int first_bit, zero_bit;
> -
> - /* Set bits should only in the range of [0, cbm_len]. */
> - if ( cbm & (~0ul << cbm_len) )
> - return false;
> -
> - /* At least one bit need to be set. */
> - if ( cbm == 0 )
> - return false;
> -
> - first_bit = find_first_bit(&cbm, cbm_len);
> - zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
> -
> - /* Set bits should be contiguous. */
> - if ( zero_bit < cbm_len &&
> - find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
> - return false;
> -
> - return true;
> -}
> -
> /* Implementation of allocation features' functions. */
> static int cat_init_feature(const struct cpuid_leaf *regs,
> struct feat_node *feat,
> @@ -431,11 +411,37 @@ static bool cat_get_feat_info(const struct feat_node *feat,
> return true;
> }
>
> +static bool cat_check_cbm(const struct feat_node *feat, unsigned long cbm)
> +{
> + unsigned int first_bit, zero_bit;
> + unsigned int cbm_len = feat->cat.cbm_len;
> +
> + /* Set bits should only in the range of [0, cbm_len]. */
> + if ( cbm & (~0ul << cbm_len) )
> + return false;
> +
> + /* At least one bit need to be set. */
> + if ( cbm == 0 )
> + return false;
You can join both checks into a single if.
> +
> + first_bit = find_first_bit(&cbm, cbm_len);
> + zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
> +
> + /* Set bits should be contiguous. */
> + if ( zero_bit < cbm_len &&
> + find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
> + return false;
> +
> + return true;
> +}
> +
> /* L3 CAT props */
> -static void l3_cat_write_msr(unsigned int cos, uint32_t val,
> - enum psr_type type)
> +static uint32_t l3_cat_write_msr(unsigned int cos, uint32_t val,
> + enum psr_type type)
> {
> wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val);
> +
> + return val;
> }
>
> static const struct feat_props l3_cat_props = {
> @@ -444,6 +450,7 @@ static const struct feat_props l3_cat_props = {
> .alt_type = PSR_TYPE_UNKNOWN,
> .get_feat_info = cat_get_feat_info,
> .write_msr = l3_cat_write_msr,
> + .check_val = cat_check_cbm,
> };
>
> /* L3 CDP props */
> @@ -458,13 +465,15 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat,
> return true;
> }
>
> -static void l3_cdp_write_msr(unsigned int cos, uint32_t val,
> - enum psr_type type)
> +static uint32_t l3_cdp_write_msr(unsigned int cos, uint32_t val,
> + enum psr_type type)
> {
> wrmsrl(((type == PSR_TYPE_L3_DATA) ?
> MSR_IA32_PSR_L3_MASK_DATA(cos) :
> MSR_IA32_PSR_L3_MASK_CODE(cos)),
> val);
> +
> + return val;
> }
>
> static const struct feat_props l3_cdp_props = {
> @@ -474,13 +483,16 @@ static const struct feat_props l3_cdp_props = {
> .alt_type = PSR_TYPE_L3_CBM,
> .get_feat_info = l3_cdp_get_feat_info,
> .write_msr = l3_cdp_write_msr,
> + .check_val = cat_check_cbm,
> };
>
> /* L2 CAT props */
> -static void l2_cat_write_msr(unsigned int cos, uint32_t val,
> - enum psr_type type)
> +static uint32_t l2_cat_write_msr(unsigned int cos, uint32_t val,
> + enum psr_type type)
> {
> wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val);
> +
> + return val;
> }
>
> static const struct feat_props l2_cat_props = {
> @@ -489,6 +501,7 @@ static const struct feat_props l2_cat_props = {
> .alt_type = PSR_TYPE_UNKNOWN,
> .get_feat_info = cat_get_feat_info,
> .write_msr = l2_cat_write_msr,
> + .check_val = cat_check_cbm,
> };
>
> /* MBA props */
> @@ -509,9 +522,23 @@ static bool mba_get_feat_info(const struct feat_node *feat,
> return true;
> }
>
> -static void mba_write_msr(unsigned int cos, uint32_t val,
> - enum psr_type type)
> +static uint32_t mba_write_msr(unsigned int cos, uint32_t val,
> + enum psr_type type)
> {
> + wrmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
> +
> + /* Read actual value set by hardware. */
> + rdmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
> +
> + return val;
> +}
> +
> +static bool mba_check_thrtl(const struct feat_node *feat, unsigned long thrtl)
> +{
> + if ( thrtl > feat->mba.thrtl_max )
> + return false;
> +
> + return true;
> }
>
> static const struct feat_props mba_props = {
> @@ -520,6 +547,7 @@ static const struct feat_props mba_props = {
> .alt_type = PSR_TYPE_UNKNOWN,
> .get_feat_info = mba_get_feat_info,
> .write_msr = mba_write_msr,
> + .check_val = mba_check_thrtl,
> };
>
> static void __init parse_psr_bool(char *s, char *value, char *feature,
> @@ -964,7 +992,7 @@ static int insert_val_into_array(uint32_t val[],
> if ( array_len < props->cos_num )
> return -ENOSPC;
>
> - if ( !psr_check_cbm(feat->cat.cbm_len, new_val) )
> + if ( !props->check_val(feat, new_val) )
> return -EINVAL;
>
> /*
> @@ -1196,25 +1224,40 @@ static unsigned int get_socket_cpu(unsigned int socket)
> struct cos_write_info
> {
> unsigned int cos;
> - struct feat_node *feature;
> + struct feat_node **features;
> const uint32_t *val;
> - const struct feat_props *props;
> + unsigned int array_len;
> + const struct feat_props **props;
> };
>
> static void do_write_psr_msrs(void *data)
Why does this function take a 'void *data' instead of 'const struct
cos_write_info *info'?
> {
> const struct cos_write_info *info = data;
> - struct feat_node *feat = info->feature;
> - const struct feat_props *props = info->props;
> - unsigned int i, cos = info->cos, cos_num = props->cos_num;
> + unsigned int i, index = 0, array_len = info->array_len, cos = info->cos;
> + const uint32_t *val_array = info->val;
>
> - for ( i = 0; i < cos_num; i++ )
> + for ( i = 0; i < ARRAY_SIZE(feat_props); i++ )
> {
> - if ( feat->cos_reg_val[cos * cos_num + i] != info->val[i] )
> + struct feat_node *feat = info->features[i];
> + const struct feat_props *props = info->props[i];
> + unsigned int cos_num, j;
> +
> + if ( !feat || !props )
> + continue;
> +
> + cos_num = props->cos_num;
> + if ( array_len < cos_num )
Not sure you need array_len, couldn't you use:
if ( index + cos_num >= info->array_len )
return;
?
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 08/15] tools: create general interfaces to support psr allocation features
2017-09-05 9:32 ` [PATCH v3 08/15] tools: create general interfaces to support psr allocation features Yi Sun
@ 2017-09-19 10:04 ` Roger Pau Monné
2017-09-20 5:45 ` Yi Sun
2017-09-22 7:01 ` Chao Peng
0 siblings, 2 replies; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 10:04 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:30PM +0800, Yi Sun wrote:
> This patch creates general interfaces in libxl to support all psr
> allocation features.
>
> Add 'LIBXL_HAVE_PSR_GENERIC' to indicate interface change.
>
> Please note, the functionality cannot work until later patches
> are applied.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - change 'LIBXL_HAVE_PSR_MBA' to 'LIBXL_HAVE_PSR_GENERIC'.
> (suggested by Roger Pau Monné)
> - 'typedef enum libxl_psr_cbm_type libxl_psr_type;' in libxl.h.
> (suggested by Roger Pau Monné and Wei Liu)
> - change 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly defined
> interfaces.
> (suggested by Roger Pau Monné)
> v2:
> - remove '_INFO' in 'libxl_psr_feat_type' and make corresponding
> changes in 'libxl_psr_hw_info'.
> (suggested by Chao Peng)
> ---
> tools/libxl/libxl.h | 33 +++++++++++++++++++++++++++++++++
> tools/libxl/libxl_psr.c | 25 +++++++++++++++++++++++++
> tools/libxl/libxl_types.idl | 22 ++++++++++++++++++++++
> 3 files changed, 80 insertions(+)
>
> diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
> index 484b5b7..9744087 100644
> --- a/tools/libxl/libxl.h
> +++ b/tools/libxl/libxl.h
> @@ -931,6 +931,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src);
> #define LIBXL_HAVE_PSR_L2_CAT 1
>
> /*
> + * LIBXL_HAVE_PSR_GENERIC
> + *
> + * If this is defined, the Memory Bandwidth Allocation feature is supported.
You should also mention that if this is defined the following public
functions are available:
libxl_psr_{set/get}_val
libxl_psr_get_hw_info
libxl_psr_hw_info_list_free
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 09/15] tools: implement the new libxc get hw info interface
2017-09-05 9:32 ` [PATCH v3 09/15] tools: implement the new libxc get hw info interface Yi Sun
@ 2017-09-19 10:15 ` Roger Pau Monné
2017-09-20 6:13 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 10:15 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:31PM +0800, Yi Sun wrote:
> This patch implements a new libxc get hw info interface and corresponding
> data structures. It also changes libxl_psr.c to call this new interface.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
> from name.
> (suggested by Roger Pau Monné)
> - remove 'info' from 'xc_cat_info' and 'xc_mba_info'.
> (suggested by Roger Pau Monné)
> - set errno in 'xc_psr_get_hw_info'.
> (suggested by Roger Pau Monné)
> - remove 'inline'.
> (suggested by Roger Pau Monné)
> - remove 'psr' from 'libxl__psr_feat_type_to_libxc_psr_feat_type' to make
> function name shorter.
> (suggested by Roger Pau Monné)
> - check 'xc_type' in 'libxl_psr_cat_get_info'.
> (suggested by Roger Pau Monné)
> v2:
> - split this patch out from a big patch in v1.
> (suggested by Wei Liu)
> - change 'CAT_INFO' and 'MBA_INFO' to 'CAT' and 'MBA'.
> (suggested by Chao Peng)
> ---
> tools/libxc/include/xenctrl.h | 30 +++++++++++++++++++++++---
> tools/libxc/xc_psr.c | 49 ++++++++++++++++++++++++++++++++-----------
> tools/libxl/libxl_psr.c | 38 +++++++++++++++++++++++++++++++--
> 3 files changed, 100 insertions(+), 17 deletions(-)
>
> diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> index c7710b8..bbdf8e2 100644
> --- a/tools/libxc/include/xenctrl.h
> +++ b/tools/libxc/include/xenctrl.h
> @@ -2458,6 +2458,31 @@ enum xc_psr_cat_type {
> };
> typedef enum xc_psr_cat_type xc_psr_cat_type;
>
> +enum xc_psr_feat_type {
> + XC_PSR_FEAT_UNKNOWN,
You don't seem to have such an unknown type in the libxl layer, any
reason you need it at the libxc layer?
> + XC_PSR_FEAT_CAT_L3,
> + XC_PSR_FEAT_CAT_L2,
> + XC_PSR_FEAT_MBA,
I think you can drop the _FEAT_ from the enum names.
> +};
> +typedef enum xc_psr_feat_type xc_psr_feat_type;
> +
> +struct xc_psr_hw_info {
> + union {
> + struct {
> + uint32_t cos_max;
> + uint32_t cbm_len;
> + bool cdp_enabled;
> + } xc_cat;
No need for the 'xc_cat', just 'cat' please (and 'mba' below).
> +
> + struct {
> + uint32_t cos_max;
> + uint32_t thrtl_max;
> + bool linear;
> + } xc_mba;
> + } u;
> +};
> +typedef struct xc_psr_hw_info xc_psr_hw_info;
> +
> int xc_psr_cmt_attach(xc_interface *xch, uint32_t domid);
> int xc_psr_cmt_detach(xc_interface *xch, uint32_t domid);
> int xc_psr_cmt_get_domain_rmid(xc_interface *xch, uint32_t domid,
> @@ -2479,9 +2504,8 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> xc_psr_cat_type type, uint32_t target,
> uint64_t *data);
> -int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
> - uint32_t *cos_max, uint32_t *cbm_len,
> - bool *cdp_enabled);
> +int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
> + xc_psr_feat_type type, xc_psr_hw_info *hw_info);
>
> int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
> int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
> diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
> index 7e1c0d6..a8a750a 100644
> --- a/tools/libxc/xc_psr.c
> +++ b/tools/libxc/xc_psr.c
> @@ -323,36 +323,61 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> return rc;
> }
>
> -int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
> - uint32_t *cos_max, uint32_t *cbm_len, bool *cdp_enabled)
> +int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
> + xc_psr_feat_type type, xc_psr_hw_info *hw_info)
> {
> int rc = -1;
> DECLARE_SYSCTL;
>
> + if ( !hw_info )
> + {
> + errno = EINVAL;
> + return rc;
> + }
> +
> sysctl.cmd = XEN_SYSCTL_psr_alloc;
> sysctl.u.psr_alloc.target = socket;
>
> - switch ( lvl )
> + switch ( type )
> {
> - case 2:
> + case XC_PSR_FEAT_CAT_L2:
> sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_l2_info;
> rc = xc_sysctl(xch, &sysctl);
> if ( !rc )
> {
> - *cos_max = sysctl.u.psr_alloc.u.cat_info.cos_max;
> - *cbm_len = sysctl.u.psr_alloc.u.cat_info.cbm_len;
> - *cdp_enabled = false;
> + hw_info->u.xc_cat.cos_max =
> + sysctl.u.psr_alloc.u.cat_info.cos_max;
> + hw_info->u.xc_cat.cbm_len =
> + sysctl.u.psr_alloc.u.cat_info.cbm_len;
> + hw_info->u.xc_cat.cdp_enabled = false;
> }
> break;
> - case 3:
> + case XC_PSR_FEAT_CAT_L3:
> sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_l3_info;
> rc = xc_sysctl(xch, &sysctl);
> if ( !rc )
> {
> - *cos_max = sysctl.u.psr_alloc.u.cat_info.cos_max;
> - *cbm_len = sysctl.u.psr_alloc.u.cat_info.cbm_len;
> - *cdp_enabled = sysctl.u.psr_alloc.u.cat_info.flags &
> - XEN_SYSCTL_PSR_ALLOC_L3_CDP;
> + hw_info->u.xc_cat.cos_max =
> + sysctl.u.psr_alloc.u.cat_info.cos_max;
> + hw_info->u.xc_cat.cbm_len =
> + sysctl.u.psr_alloc.u.cat_info.cbm_len;
> + hw_info->u.xc_cat.cdp_enabled =
> + sysctl.u.psr_alloc.u.cat_info.flags &
> + XEN_SYSCTL_PSR_ALLOC_L3_CDP;
> + }
> + break;
> + case XC_PSR_FEAT_MBA:
> + sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_mba_info;
> + rc = xc_sysctl(xch, &sysctl);
> + if ( !rc )
> + {
> + hw_info->u.xc_mba.cos_max =
> + sysctl.u.psr_alloc.u.mba_info.cos_max;
> + hw_info->u.xc_mba.thrtl_max =
> + sysctl.u.psr_alloc.u.mba_info.thrtl_max;
> + hw_info->u.xc_mba.linear =
> + sysctl.u.psr_alloc.u.mba_info.flags &
> + XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
> }
Would it help to prevent line breaks to change the indentation above
to:
rc = xc_sysctl(...);
if ( rc )
break;
hw_info->u....
?
> break;
> default:
> diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> index 4a6978e..dd412cc 100644
> --- a/tools/libxl/libxl_psr.c
> +++ b/tools/libxl/libxl_psr.c
> @@ -361,6 +361,27 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> return rc;
> }
>
> +static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
> + libxl_psr_feat_type type, unsigned int lvl)
> +{
> + xc_psr_feat_type xc_type = XC_PSR_FEAT_UNKNOWN;
> +
> + switch (type) {
> + case LIBXL_PSR_FEAT_TYPE_CAT:
> + if (lvl == 3)
> + xc_type = XC_PSR_FEAT_CAT_L3;
> + if (lvl == 2)
> + xc_type = XC_PSR_FEAT_CAT_L2;
> + break;
> + case LIBXL_PSR_FEAT_TYPE_MBA:
> + xc_type = XC_PSR_FEAT_MBA;
> + default:
> + break;
assert?
libxl_psr_feat_type cannot have any other value apart from the two
that you list above.
> + }
> +
> + return xc_type;
> +}
> +
> int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> unsigned int *nr, unsigned int lvl)
> {
> @@ -369,6 +390,8 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> int i = 0, socketid, nr_sockets;
> libxl_bitmap socketmap;
> libxl_psr_cat_info *ptr;
> + xc_psr_hw_info hw_info;
> + xc_psr_feat_type xc_type;
>
> libxl_bitmap_init(&socketmap);
>
> @@ -385,16 +408,27 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> goto out;
> }
>
> + xc_type = libxl__feat_type_to_libxc_feat_type(LIBXL_PSR_FEAT_TYPE_CAT, lvl);
> + if (xc_type == XC_PSR_FEAT_UNKNOWN) {
> + LOG(ERROR, "feature type or lvl is wrong");
> + rc = ERROR_FAIL;
> + goto out;
> + }
> +
> ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
>
> libxl_for_each_set_bit(socketid, socketmap) {
> ptr[i].id = socketid;
> - if (xc_psr_cat_get_info(ctx->xch, socketid, lvl, &ptr[i].cos_max,
> - &ptr[i].cbm_len, &ptr[i].cdp_enabled)) {
> + if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
It might be nice to LOG the errno here, or else you lose it AFAICT.
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 10/15] tools: implement the new libxl get hw info interface
2017-09-05 9:32 ` [PATCH v3 10/15] tools: implement the new libxl " Yi Sun
@ 2017-09-19 10:28 ` Roger Pau Monné
2017-09-20 6:20 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 10:28 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:32PM +0800, Yi Sun wrote:
> This patch implements the new libxl get hw info interface,
> 'libxl_psr_get_hw_info', which is suitable to all psr allocation
> features. It also implements corresponding list free function,
> 'libxl_psr_hw_info_list_free' and make 'libxl_psr_cat_get_info' to call
^makes ^call
> 'libxl_psr_get_hw_info' to avoid redundant codes in libxl_psr.c.
^code
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - remove casting.
> (suggested by Roger Pau Monné)
> - remove inline.
> (suggested by Roger Pau Monné)
> - change 'libxc__psr_hw_info_to_libxl_psr_hw_info' to
> 'libxl__xc_hw_info_to_libxl_hw_info'.
> (suggested by Roger Pau Monné)
> - remove '_hw' from parameter names.
> (suggested by Roger Pau Monné)
> - change some 'LOGE' to 'LOG'.
> (suggested by Roger Pau Monné)
> - check returned 'xc_type' and remove redundant 'lvl' check.
> (suggested by Roger Pau Monné)
> v2:
> - split this patch out from a big patch in v1.
> (suggested by Wei Liu)
> - change 'CAT_INFO'/'MBA_INFO' to 'CAT' and 'MBA. Also the libxl structure
> name 'cat_info'/'mba_info' is changed to 'cat'/'mba'.
> (suggested by Chao Peng)
> - call 'libxl_psr_hw_info_list_free' in 'libxl_psr_cat_get_info' to free
> allocated resources.
> (suggested by Chao Peng)
> ---
> tools/libxl/libxl_psr.c | 145 ++++++++++++++++++++++++++++++++++++------------
> 1 file changed, 108 insertions(+), 37 deletions(-)
>
> diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> index dd412cc..d534ec2 100644
> --- a/tools/libxl/libxl_psr.c
> +++ b/tools/libxl/libxl_psr.c
> @@ -382,60 +382,49 @@ static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
> return xc_type;
> }
>
> +static int libxl__hw_info_to_libxl_cat_info(
> + libxl_psr_feat_type type, libxl_psr_hw_info *hw_info,
> + libxl_psr_cat_info *cat_info)
> +{
> + if (type != LIBXL_PSR_FEAT_TYPE_CAT)
> + return ERROR_INVAL;
Since this is an internal libxl function, is there any possible valid
scenario where this function is called with type !=
LIBXL_PSR_FEAT_TYPE_CAT?
If not this should be an assert instead, and the function could return
void.
> +
> + cat_info->id = hw_info->id;
> + cat_info->cos_max = hw_info->u.cat.cos_max;
> + cat_info->cbm_len = hw_info->u.cat.cbm_len;
> + cat_info->cdp_enabled = hw_info->u.cat.cdp_enabled;
> +
> + return 0;
> +}
> +
> int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> unsigned int *nr, unsigned int lvl)
> {
> GC_INIT(ctx);
> int rc;
> - int i = 0, socketid, nr_sockets;
> - libxl_bitmap socketmap;
> + unsigned int i;
> + libxl_psr_hw_info *hw_info;
> libxl_psr_cat_info *ptr;
> - xc_psr_hw_info hw_info;
> - xc_psr_feat_type xc_type;
> -
> - libxl_bitmap_init(&socketmap);
>
> - rc = libxl__count_physical_sockets(gc, &nr_sockets);
> - if (rc) {
> - LOGE(ERROR, "failed to get system socket count");
> + rc = libxl_psr_get_hw_info(ctx, &hw_info, nr, LIBXL_PSR_FEAT_TYPE_CAT, lvl);
> + if (rc)
> goto out;
> - }
>
> - libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
> - rc = libxl_get_online_socketmap(ctx, &socketmap);
> - if (rc < 0) {
> - LOGE(ERROR, "failed to get available sockets");
> - goto out;
> - }
> -
> - xc_type = libxl__feat_type_to_libxc_feat_type(LIBXL_PSR_FEAT_TYPE_CAT, lvl);
> - if (xc_type == XC_PSR_FEAT_UNKNOWN) {
> - LOG(ERROR, "feature type or lvl is wrong");
> - rc = ERROR_FAIL;
> - goto out;
> - }
> + ptr = libxl__malloc(NOGC, *nr * sizeof(libxl_psr_cat_info));
>
> - ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
> -
> - libxl_for_each_set_bit(socketid, socketmap) {
> - ptr[i].id = socketid;
> - if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
> + for (i = 0; i < *nr; i++) {
> + if (libxl__hw_info_to_libxl_cat_info(LIBXL_PSR_FEAT_TYPE_CAT,
> + &hw_info[i], &ptr[i])) {
Please use rc here:
rc = libxl__hw_info_to_libxl_cat_info(...);
if (rc) {
...
This has the bonus of not losing the error code returned by
libxl__hw_info_to_libxl_cat_info.
> + libxl_psr_hw_info_list_free(hw_info, *nr);
> rc = ERROR_FAIL;
> free(ptr);
> goto out;
> }
> -
> - ptr[i].cos_max = hw_info.u.xc_cat.cos_max;
> - ptr[i].cbm_len = hw_info.u.xc_cat.cbm_len;
> - ptr[i].cdp_enabled = hw_info.u.xc_cat.cdp_enabled;
> -
> - i++;
> }
>
> *info = ptr;
> - *nr = i;
> + libxl_psr_hw_info_list_free(hw_info, *nr);
> out:
> - libxl_bitmap_dispose(&socketmap);
> GC_FREE;
> return rc;
> }
> @@ -476,15 +465,97 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
> return ERROR_FAIL;
> }
>
> +static int libxl__xc_hw_info_to_libxl_hw_info(
> + libxl_psr_feat_type type, xc_psr_hw_info *xc_info,
> + libxl_psr_hw_info *xl_info)
> +{
> + switch (type) {
> + case LIBXL_PSR_FEAT_TYPE_CAT:
> + xl_info->u.cat.cos_max = xc_info->u.xc_cat.cos_max;
> + xl_info->u.cat.cbm_len = xc_info->u.xc_cat.cbm_len;
> + xl_info->u.cat.cdp_enabled = xc_info->u.xc_cat.cdp_enabled;
> + break;
> + case LIBXL_PSR_FEAT_TYPE_MBA:
> + xl_info->u.mba.cos_max = xc_info->u.xc_mba.cos_max;
> + xl_info->u.mba.thrtl_max = xc_info->u.xc_mba.thrtl_max;
> + xl_info->u.mba.linear = xc_info->u.xc_mba.linear;
> + break;
> + default:
> + return ERROR_INVAL;
> + }
> +
> + return 0;
> +}
> +
> int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
> unsigned int *nr, libxl_psr_feat_type type,
> unsigned int lvl)
> {
> - return ERROR_FAIL;
> + GC_INIT(ctx);
> + int rc, nr_sockets;
> + unsigned int i = 0, socketid;
> + libxl_bitmap socketmap;
> + libxl_psr_hw_info *ptr;
> + xc_psr_feat_type xc_type;
> + xc_psr_hw_info hw_info;
> +
> + libxl_bitmap_init(&socketmap);
> +
> + xc_type = libxl__feat_type_to_libxc_feat_type(type, lvl);
> + if (xc_type == XC_PSR_FEAT_UNKNOWN) {
> + LOG(ERROR, "feature type or lvl is wrong");
> + rc = ERROR_FAIL;
> + goto out;
> + }
> +
> + rc = libxl__count_physical_sockets(gc, &nr_sockets);
> + if (rc) {
> + LOG(ERROR, "failed to get system socket count");
> + goto out;
> + }
> +
> + libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
> + rc = libxl_get_online_socketmap(ctx, &socketmap);
> + if (rc < 0) {
> + LOGE(ERROR, "failed to get available sockets");
> + goto out;
> + }
> +
> + ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_hw_info));
> +
> + libxl_for_each_set_bit(socketid, socketmap) {
> + ptr[i].id = socketid;
> + if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
> + rc = ERROR_FAIL;
> + free(ptr);
> + goto out;
> + }
> +
> + if (libxl__xc_hw_info_to_libxl_hw_info(type, &hw_info, &ptr[i])) {
> + LOGE(ERROR, "Input type %d is wrong!\n", type);
> + rc = ERROR_FAIL;
> + free(ptr);
> + goto out;
> + }
> + i++;
> + }
> +
> + *info = ptr;
> + *nr = i;
> +out:
> + libxl_bitmap_dispose(&socketmap);
> + GC_FREE;
> + return rc;
> }
>
> void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr)
> {
> + unsigned int i;
> +
> + for (i = 0; i < nr; i++)
> + libxl_psr_hw_info_dispose(&list[i]);
> + free(list);
Don't you also need a libxl_psr_cat_info_list_free? Or am I missing
something?
> }
>
> /*
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 11/15] tools: implement the new xl get hw info interface
2017-09-05 9:32 ` [PATCH v3 11/15] tools: implement the new xl " Yi Sun
@ 2017-09-19 10:32 ` Roger Pau Monné
2017-09-20 6:23 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 10:32 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:33PM +0800, Yi Sun wrote:
> This patch implements a new xl get HW info interface. A new argument
> is added for psr-hwinfo command to get and show MBA HW info.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - change the format string of printf in 'psr_mba_hwinfo'.
> (suggested by Roger Pau Monné)
> - add 'const' for 'opts[]' in 'main_psr_hwinfo'.
> (suggested by Roger Pau Monné)
> v2:
> - split out this patch from a big patch in v1.
> (suggested by Wei Liu)
> - change 'MBA_INFO' to 'MBA'. Also, change 'mba_info' to 'mba'.
> (suggested by Chao Peng)
> ---
> tools/xl/xl_cmdtable.c | 1 +
> tools/xl/xl_psr.c | 40 +++++++++++++++++++++++++++++++++++++---
> 2 files changed, 38 insertions(+), 3 deletions(-)
>
> diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
> index 6baaed2..a01245d 100644
> --- a/tools/xl/xl_cmdtable.c
> +++ b/tools/xl/xl_cmdtable.c
> @@ -524,6 +524,7 @@ struct cmd_spec cmd_table[] = {
> "[options]",
> "-m, --cmt Show Cache Monitoring Technology (CMT) hardware info\n"
> "-a, --cat Show Cache Allocation Technology (CAT) hardware info\n"
> + "-b, --mba Show Memory Bandwidth Allocation (MBA) hardware info\n"
> },
> { "psr-cmt-attach",
> &main_psr_cmt_attach, 0, 1,
> diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
> index ef00048..40269b4 100644
> --- a/tools/xl/xl_psr.c
> +++ b/tools/xl/xl_psr.c
> @@ -475,6 +475,32 @@ static int psr_l2_cat_hwinfo(void)
> return rc;
> }
>
> +static int psr_mba_hwinfo(void)
> +{
> + int rc;
> + unsigned int i, nr;
> + libxl_psr_hw_info *info;
> +
> + rc = libxl_psr_get_hw_info(ctx, &info, &nr,
> + LIBXL_PSR_FEAT_TYPE_MBA, 0);
> + if (rc)
> + return rc;
> +
> + printf("Memory Bandwidth Allocation (MBA):\n");
> +
> + for (i = 0; i < nr; i++) {
> + printf("Socket ID : %u\n", info[i].id);
> + printf("Linear Mode : %s\n",
> + info[i].u.mba.linear ? "Enabled" : "Disabled");
> + printf("Maximum COS : %u\n", info[i].u.mba.cos_max);
> + printf("Maximum Throttling Value: %u\n", info[i].u.mba.thrtl_max);
> + printf("Default Throttling Value: %u\n", 0);
What's the point in printing a default value if it's always 0? Ie:
this can be on the docs, but I don't think is meaningful here.
Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type'
2017-09-05 9:32 ` [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
@ 2017-09-19 10:34 ` Roger Pau Monné
2017-09-20 6:25 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 10:34 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:34PM +0800, Yi Sun wrote:
> This patch renames 'xc_psr_cat_type' to 'xc_psr_type' so that
> the structure name is common for all allocation features.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> Acked-by: Wei Liu <wei.liu2@citrix.com>
> Reviewed-by: Chao Peng <chao.p.peng@linux.intel.com>
> ---
> v3:
> - change 'xc_psr_val_type' to 'xc_psr_type'.
> (suggested by Roger Pau Monné)
> ---
> tools/libxc/include/xenctrl.h | 8 ++++----
> tools/libxc/xc_psr.c | 4 ++--
> tools/libxl/libxl_psr.c | 12 ++++++------
> 3 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> index bbdf8e2..63b92d2 100644
> --- a/tools/libxc/include/xenctrl.h
> +++ b/tools/libxc/include/xenctrl.h
> @@ -2450,13 +2450,13 @@ enum xc_psr_cmt_type {
> };
> typedef enum xc_psr_cmt_type xc_psr_cmt_type;
>
> -enum xc_psr_cat_type {
> +enum xc_psr_type {
> XC_PSR_CAT_L3_CBM = 1,
> XC_PSR_CAT_L3_CBM_CODE = 2,
> XC_PSR_CAT_L3_CBM_DATA = 3,
> XC_PSR_CAT_L2_CBM = 4,
> };
> -typedef enum xc_psr_cat_type xc_psr_cat_type;
> +typedef enum xc_psr_type xc_psr_type;
>
> enum xc_psr_feat_type {
> XC_PSR_FEAT_UNKNOWN,
> @@ -2499,10 +2499,10 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
> int xc_psr_cmt_enabled(xc_interface *xch);
>
> int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_cat_type type, uint32_t target,
> + xc_psr_type type, uint32_t target,
> uint64_t data);
> int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_cat_type type, uint32_t target,
> + xc_psr_type type, uint32_t target,
> uint64_t *data);
> int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
> xc_psr_feat_type type, xc_psr_hw_info *hw_info);
> diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
> index a8a750a..80642a2 100644
> --- a/tools/libxc/xc_psr.c
> +++ b/tools/libxc/xc_psr.c
> @@ -249,7 +249,7 @@ int xc_psr_cmt_enabled(xc_interface *xch)
> return 0;
> }
> int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_cat_type type, uint32_t target,
> + xc_psr_type type, uint32_t target,
> uint64_t data)
> {
> DECLARE_DOMCTL;
> @@ -284,7 +284,7 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> }
>
> int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_cat_type type, uint32_t target,
> + xc_psr_type type, uint32_t target,
> uint64_t *data)
> {
> int rc;
> diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> index d534ec2..c8d2921 100644
> --- a/tools/libxl/libxl_psr.c
> +++ b/tools/libxl/libxl_psr.c
> @@ -303,11 +303,11 @@ out:
> return rc;
> }
>
> -static inline xc_psr_cat_type libxl__psr_cbm_type_to_libxc_psr_cat_type(
> +static inline xc_psr_type libxl__psr_cbm_type_to_libxc_psr_type(
> libxl_psr_cbm_type type)
> {
> - BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_cat_type));
> - return (xc_psr_cat_type)type;
> + BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_type));
> + return (xc_psr_type)type;
> }
>
> int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
> @@ -325,12 +325,12 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
> }
>
> libxl_for_each_set_bit(socketid, *target_map) {
> - xc_psr_cat_type xc_type;
> + xc_psr_type xc_type;
>
> if (socketid >= nr_sockets)
> break;
>
> - xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
> + xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
You can place this with the variable declaration:
xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
Thanks, Roger.
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command
2017-09-05 9:32 ` [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command Yi Sun
@ 2017-09-19 11:02 ` Roger Pau Monné
2017-09-20 6:46 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 11:02 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:35PM +0800, Yi Sun wrote:
> This patch implements generic get value interfaces in libxc and libxl.
> It also refactors the get value flow in xl to make it be suitable for all
> allocation features. Based on that, a new MBA get value command is added in xl.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> Acked-by: Wei Liu <wei.liu2@citrix.com>
> ---
> v3:
> - replace 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly defined
> interfaces.
> (suggested by Roger Pau Monné)
> v2:
> - change 'CAT_INFO'/'MBA_INFO' to 'CAT'/'MBA'. The related structure names
> are changed too.
> (suggested by Chao Peng)
> ---
> tools/libxc/include/xenctrl.h | 7 +-
> tools/libxc/xc_psr.c | 9 +-
> tools/libxl/libxl_psr.c | 59 +++++++++-----
> tools/xl/xl.h | 1 +
> tools/xl/xl_cmdtable.c | 5 ++
> tools/xl/xl_psr.c | 185 ++++++++++++++++++++++++++++++------------
> 6 files changed, 184 insertions(+), 82 deletions(-)
>
> diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> index 63b92d2..eef06be 100644
> --- a/tools/libxc/include/xenctrl.h
> +++ b/tools/libxc/include/xenctrl.h
> @@ -2455,6 +2455,7 @@ enum xc_psr_type {
> XC_PSR_CAT_L3_CBM_CODE = 2,
> XC_PSR_CAT_L3_CBM_DATA = 3,
> XC_PSR_CAT_L2_CBM = 4,
> + XC_PSR_MBA_THRTL = 5,
> };
> typedef enum xc_psr_type xc_psr_type;
>
> @@ -2501,9 +2502,9 @@ int xc_psr_cmt_enabled(xc_interface *xch);
> int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> xc_psr_type type, uint32_t target,
> uint64_t data);
> -int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_type type, uint32_t target,
> - uint64_t *data);
> +int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
> + xc_psr_type type, uint32_t target,
> + uint64_t *data);
> int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
> xc_psr_feat_type type, xc_psr_hw_info *hw_info);
>
> diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
> index 80642a2..2f0eed9 100644
> --- a/tools/libxc/xc_psr.c
> +++ b/tools/libxc/xc_psr.c
> @@ -283,9 +283,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> return do_domctl(xch, &domctl);
> }
>
> -int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_type type, uint32_t target,
> - uint64_t *data)
> +int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
> + xc_psr_type type, uint32_t target,
> + uint64_t *data)
> {
> int rc;
> DECLARE_DOMCTL;
> @@ -305,6 +305,9 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
> case XC_PSR_CAT_L2_CBM:
> cmd = XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM;
> break;
> + case XC_PSR_MBA_THRTL:
> + cmd = XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL;
> + break;
> default:
> errno = EINVAL;
> return -1;
> diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> index c8d2921..78d5bc5 100644
> --- a/tools/libxl/libxl_psr.c
> +++ b/tools/libxl/libxl_psr.c
> @@ -71,16 +71,30 @@ static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
> LOGE(ERROR, "%s", msg);
> }
>
> -static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> +static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
> + int err,
> + libxl_psr_type type)
> {
> + /*
> + * Index is 'libxl_psr_type' so we set two 'CDP' to correspond to
> + * DATA and CODE.
> + */
> + const char * const feat_name[6] = {
The explicit '6' is not needed.
> + "UNKNOWN",
> + "L3 CAT",
> + "CDP",
> + "CDP",
> + "L2 CAT",
> + "MBA",
I'm not sure whether you want to use designated initializers here, in
case someone decides to change the order of the xc_psr_type enum or
the order here. ie:
feat_name[] = {
[XC_PSR_CAT_L3_CBM] = "L3 CAT",
[XC_PSR_CAT_L3_CBM_CODE..XC_PSR_CAT_L3_CBM_DATA] = "CDP",
...
}
> + };
> char *msg;
>
> switch (err) {
> case ENODEV:
> - msg = "CAT is not supported in this system";
> + msg = "is not supported in this system";
> break;
> case ENOENT:
> - msg = "CAT is not enabled on the socket";
> + msg = "is not enabled on the socket";
> break;
> case EOVERFLOW:
> msg = "no free COS available";
> @@ -106,7 +120,7 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> return;
> }
>
> - LOGE(ERROR, "%s", msg);
> + LOGE(ERROR, "%s: %s", feat_name[type], msg);
I don't think you should use LOGE here, but rather LOG. LOGE should be
used when errno is set, which I don't think is the case here.
> }
>
> static int libxl__pick_socket_cpu(libxl__gc *gc, uint32_t socketid)
> @@ -303,10 +317,10 @@ out:
> return rc;
> }
>
> -static inline xc_psr_type libxl__psr_cbm_type_to_libxc_psr_type(
> - libxl_psr_cbm_type type)
> +static inline xc_psr_type libxl__psr_type_to_libxc_psr_type(
> + libxl_psr_type type)
> {
> - BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_type));
> + BUILD_BUG_ON(sizeof(libxl_psr_type) != sizeof(xc_psr_type));
> return (xc_psr_type)type;
> }
>
> @@ -330,10 +344,10 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
> if (socketid >= nr_sockets)
> break;
>
> - xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
> + xc_type = libxl__psr_type_to_libxc_psr_type(type);
> if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
> socketid, cbm)) {
> - libxl__psr_cat_log_err_msg(gc, errno);
> + libxl__psr_alloc_log_err_msg(gc, errno, type);
> rc = ERROR_FAIL;
> }
> }
> @@ -347,18 +361,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> libxl_psr_cbm_type type, uint32_t target,
> uint64_t *cbm_r)
> {
> - GC_INIT(ctx);
> - int rc = 0;
> - xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
> -
> - if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
> - target, cbm_r)) {
> - libxl__psr_cat_log_err_msg(gc, errno);
> - rc = ERROR_FAIL;
> - }
> -
> - GC_FREE;
> - return rc;
> + return libxl_psr_get_val(ctx, domid, type, target, cbm_r);
> }
You could even move this to libxl.h as a static function IMHO.
>
> static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
> @@ -462,7 +465,19 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
> libxl_psr_type type, unsigned int target,
> uint64_t *val)
> {
> - return ERROR_FAIL;
> + GC_INIT(ctx);
> + int rc = 0;
> +
> + xc_psr_type xc_type = libxl__psr_type_to_libxc_psr_type(type);
> +
> + if (xc_psr_get_domain_data(ctx->xch, domid, xc_type,
> + target, val)) {
> + libxl__psr_alloc_log_err_msg(gc, errno, type);
> + rc = ERROR_FAIL;
> + }
> +
> + GC_FREE;
> + return rc;
> }
>
> static int libxl__xc_hw_info_to_libxl_hw_info(
> diff --git a/tools/xl/xl.h b/tools/xl/xl.h
> index 8d7b957..3389df9 100644
> --- a/tools/xl/xl.h
> +++ b/tools/xl/xl.h
> @@ -204,6 +204,7 @@ int main_psr_cmt_detach(int argc, char **argv);
> int main_psr_cmt_show(int argc, char **argv);
> int main_psr_cat_cbm_set(int argc, char **argv);
> int main_psr_cat_show(int argc, char **argv);
> +int main_psr_mba_show(int argc, char **argv);
> #endif
> int main_qemu_monitor_command(int argc, char **argv);
>
> diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
> index a01245d..cdc2349 100644
> --- a/tools/xl/xl_cmdtable.c
> +++ b/tools/xl/xl_cmdtable.c
> @@ -560,6 +560,11 @@ struct cmd_spec cmd_table[] = {
> "[options] <Domain>",
> "-l <level> Specify the cache level to process, otherwise L3 cache is processed\n"
> },
> + { "psr-mba-show",
> + &main_psr_mba_show, 0, 1,
> + "Show Memory Bandwidth Allocation information",
> + "<Domain>",
> + },
> #endif
> { "usbctrl-attach",
> &main_usbctrl_attach, 0, 1,
> diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
> index 40269b4..46b7788 100644
> --- a/tools/xl/xl_psr.c
> +++ b/tools/xl/xl_psr.c
> @@ -327,19 +327,27 @@ out:
> return rc;
> }
>
> -static void psr_cat_print_one_domain_cbm_type(uint32_t domid, uint32_t socketid,
> - libxl_psr_cbm_type type)
> +static void psr_print_one_domain_val_type(uint32_t domid,
> + libxl_psr_hw_info *info,
> + libxl_psr_type type)
> {
> - uint64_t cbm;
> + uint64_t val;
>
> - if (!libxl_psr_cat_get_cbm(ctx, domid, type, socketid, &cbm))
> - printf("%#16"PRIx64, cbm);
> + if (!libxl_psr_get_val(ctx, domid, type, info->id, &val))
> + {
> + if (type == LIBXL_PSR_CBM_TYPE_MBA_THRTL && info->u.mba.linear)
> + printf("%16"PRIu64, val);
> + else
> + printf("%#16"PRIx64, val);
> + }
> else
> printf("%16s", "error");
> }
>
> -static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
> - bool cdp_enabled, unsigned int lvl)
> +static void psr_print_one_domain_val(uint32_t domid,
> + libxl_psr_hw_info *info,
> + libxl_psr_feat_type type,
> + unsigned int lvl)
> {
> char *domain_name;
>
> @@ -347,106 +355,154 @@ static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
> printf("%5d%25s", domid, domain_name);
> free(domain_name);
>
> - switch (lvl) {
> - case 3:
> - if (!cdp_enabled) {
> - psr_cat_print_one_domain_cbm_type(domid, socketid,
> + switch (type) {
> + case LIBXL_PSR_FEAT_TYPE_CAT:
> + switch (lvl) {
> + case 3:
> + if (!info->u.cat.cdp_enabled) {
> + psr_print_one_domain_val_type(domid, info,
> LIBXL_PSR_CBM_TYPE_L3_CBM);
> - } else {
> - psr_cat_print_one_domain_cbm_type(domid, socketid,
> + } else {
> + psr_print_one_domain_val_type(domid, info,
> LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
> - psr_cat_print_one_domain_cbm_type(domid, socketid,
> + psr_print_one_domain_val_type(domid, info,
> LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
> - }
> - break;
> - case 2:
> - psr_cat_print_one_domain_cbm_type(domid, socketid,
> + }
> + break;
> +
> + case 2:
> + psr_print_one_domain_val_type(domid, info,
> LIBXL_PSR_CBM_TYPE_L2_CBM);
> + break;
> +
> + default:
> + printf("Input lvl %d is wrong!", lvl);
> + }
> break;
> - default:
> - printf("Input lvl %d is wrong!", lvl);
> +
> + case LIBXL_PSR_FEAT_TYPE_MBA:
> + psr_print_one_domain_val_type(domid, info,
> + LIBXL_PSR_CBM_TYPE_MBA_THRTL);
> break;
> }
>
> printf("\n");
> }
>
> -static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socketid,
> - bool cdp_enabled, unsigned int lvl)
> +static int psr_print_domain_val(uint32_t domid,
> + libxl_psr_hw_info *info,
> + libxl_psr_feat_type type,
> + unsigned int lvl)
> {
> int i, nr_domains;
> libxl_dominfo *list;
>
> if (domid != INVALID_DOMID) {
> - psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled, lvl);
> + psr_print_one_domain_val(domid, info, type, lvl);
> return 0;
> }
>
> if (!(list = libxl_list_domain(ctx, &nr_domains))) {
> - fprintf(stderr, "Failed to get domain list for cbm display\n");
> - return -1;
> + fprintf(stderr, "Failed to get domain list for value display\n");
> + return EXIT_FAILURE;
> }
>
> for (i = 0; i < nr_domains; i++)
> - psr_cat_print_one_domain_cbm(list[i].domid, socketid, cdp_enabled, lvl);
> + psr_print_one_domain_val(list[i].domid, info, type, lvl);
> libxl_dominfo_list_free(list, nr_domains);
>
> return 0;
> }
>
> -static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
> - unsigned int lvl)
> +static int psr_print_socket(uint32_t domid,
> + libxl_psr_hw_info *info,
> + libxl_psr_feat_type type,
> + unsigned int lvl)
> {
> - int rc;
> - uint32_t l3_cache_size;
> -
> printf("%-16s: %u\n", "Socket ID", info->id);
>
> - /* So far, CMT only supports L3 cache. */
> - if (lvl == 3) {
> - rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
> - if (rc) {
> - fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
> - info->id);
> - return -1;
> + switch (type) {
> + case LIBXL_PSR_FEAT_TYPE_CAT:
> + {
> + int rc;
> + uint32_t l3_cache_size;
> +
> + /* So far, CMT only supports L3 cache. */
> + if (lvl == 3) {
Shouldn't you print some kind of error message if lvl != 3? Or is it
expected that this function will be called with lvl != 3 and it should
be ignored?
Thanks, Roger.
_______________________________________________
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 14/15] tools: implement new generic set value interface and MBA set value command
2017-09-05 9:32 ` [PATCH v3 14/15] tools: implement new generic set value interface and MBA set " Yi Sun
@ 2017-09-19 11:30 ` Roger Pau Monné
2017-09-20 7:25 ` Yi Sun
2017-09-20 16:10 ` Wei Liu
0 siblings, 2 replies; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 11:30 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:36PM +0800, Yi Sun wrote:
> This patch implements new generic set value interfaces in libxc and libxl.
> These interfaces are suitable for all allocation features. It also adds a
> new MBA set value command in xl.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v3:
> - add 'const' for 'opts[]' in 'main_psr_mba_set'.
> (suggested by Roger Pau Monné)
> - replace 'libxl_psr_cbm_type' to 'libxl_psr_type' for newly defined
> interfaces.
> (suggested by Roger Pau Monné)
> ---
> tools/libxc/include/xenctrl.h | 6 ++---
> tools/libxc/xc_psr.c | 9 ++++---
> tools/libxl/libxl_psr.c | 56 +++++++++++++++++++++----------------------
> tools/xl/xl.h | 1 +
> tools/xl/xl_cmdtable.c | 6 +++++
> tools/xl/xl_psr.c | 55 ++++++++++++++++++++++++++++++++++++++++++
> 6 files changed, 99 insertions(+), 34 deletions(-)
>
> diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> index eef06be..21dac2f 100644
> --- a/tools/libxc/include/xenctrl.h
> +++ b/tools/libxc/include/xenctrl.h
> @@ -2499,9 +2499,9 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
> uint64_t *tsc);
> int xc_psr_cmt_enabled(xc_interface *xch);
>
> -int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_type type, uint32_t target,
> - uint64_t data);
> +int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
> + xc_psr_type type, uint32_t target,
> + uint64_t data);
> int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
> xc_psr_type type, uint32_t target,
> uint64_t *data);
> diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
> index 2f0eed9..e53b5f5 100644
> --- a/tools/libxc/xc_psr.c
> +++ b/tools/libxc/xc_psr.c
> @@ -248,9 +248,9 @@ int xc_psr_cmt_enabled(xc_interface *xch)
>
> return 0;
> }
> -int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> - xc_psr_type type, uint32_t target,
> - uint64_t data)
> +int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
> + xc_psr_type type, uint32_t target,
> + uint64_t data)
> {
> DECLARE_DOMCTL;
> uint32_t cmd;
> @@ -269,6 +269,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
> case XC_PSR_CAT_L2_CBM:
> cmd = XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM;
> break;
> + case XC_PSR_MBA_THRTL:
> + cmd = XEN_DOMCTL_PSR_ALLOC_SET_MBA_THRTL;
> + break;
> default:
> errno = EINVAL;
> return -1;
> diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> index 78d5bc5..d3c3d42 100644
> --- a/tools/libxl/libxl_psr.c
> +++ b/tools/libxl/libxl_psr.c
> @@ -328,33 +328,7 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
> libxl_psr_cbm_type type, libxl_bitmap *target_map,
> uint64_t cbm)
> {
> - GC_INIT(ctx);
> - int rc;
> - int socketid, nr_sockets;
> -
> - rc = libxl__count_physical_sockets(gc, &nr_sockets);
> - if (rc) {
> - LOGED(ERROR, domid, "failed to get system socket count");
> - goto out;
> - }
> -
> - libxl_for_each_set_bit(socketid, *target_map) {
> - xc_psr_type xc_type;
> -
> - if (socketid >= nr_sockets)
> - break;
> -
> - xc_type = libxl__psr_type_to_libxc_psr_type(type);
> - if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
> - socketid, cbm)) {
> - libxl__psr_alloc_log_err_msg(gc, errno, type);
> - rc = ERROR_FAIL;
> - }
> - }
> -
> -out:
> - GC_FREE;
> - return rc;
> + return libxl_psr_set_val(ctx, domid, type, target_map, cbm);
> }
>
> int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> @@ -458,7 +432,33 @@ int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
> libxl_psr_type type, libxl_bitmap *target_map,
> uint64_t val)
> {
> - return ERROR_FAIL;
> + GC_INIT(ctx);
> + int rc;
> + int socketid, nr_sockets;
You could fit them all in a single line.
> + rc = libxl__count_physical_sockets(gc, &nr_sockets);
> + if (rc) {
> + LOG(ERROR, "failed to get system socket count");
> + goto out;
> + }
> +
> + libxl_for_each_set_bit(socketid, *target_map) {
> + xc_psr_type xc_type;
> +
> + if (socketid >= nr_sockets)
> + break;
> +
> + xc_type = libxl__psr_type_to_libxc_psr_type(type);
> + if (xc_psr_set_domain_data(ctx->xch, domid, xc_type,
> + socketid, val)) {
> + libxl__psr_alloc_log_err_msg(gc, errno, type);
> + rc = ERROR_FAIL;
> + }
> + }
> +
> +out:
> + GC_FREE;
> + return rc;
> }
>
> int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
> diff --git a/tools/xl/xl.h b/tools/xl/xl.h
> index 3389df9..3f99b6b 100644
> --- a/tools/xl/xl.h
> +++ b/tools/xl/xl.h
> @@ -204,6 +204,7 @@ int main_psr_cmt_detach(int argc, char **argv);
> int main_psr_cmt_show(int argc, char **argv);
> int main_psr_cat_cbm_set(int argc, char **argv);
> int main_psr_cat_show(int argc, char **argv);
> +int main_psr_mba_set(int argc, char **argv);
> int main_psr_mba_show(int argc, char **argv);
> #endif
> int main_qemu_monitor_command(int argc, char **argv);
> diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
> index cdc2349..9d45d3b 100644
> --- a/tools/xl/xl_cmdtable.c
> +++ b/tools/xl/xl_cmdtable.c
> @@ -560,6 +560,12 @@ struct cmd_spec cmd_table[] = {
> "[options] <Domain>",
> "-l <level> Specify the cache level to process, otherwise L3 cache is processed\n"
> },
> + { "psr-mba-set",
> + &main_psr_mba_set, 0, 1,
> + "Set throttling value (THRTL) for a domain",
> + "[options] <Domain> <THRTL>",
> + "-s <socket> Specify the socket to process, otherwise all sockets are processed\n"
> + },
> { "psr-mba-show",
> &main_psr_mba_show, 0, 1,
> "Show Memory Bandwidth Allocation information",
> diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
> index 46b7788..a648b1a 100644
> --- a/tools/xl/xl_psr.c
> +++ b/tools/xl/xl_psr.c
> @@ -552,6 +552,61 @@ int main_psr_mba_show(int argc, char **argv)
> return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_MBA, 0);
> }
>
> +int main_psr_mba_set(int argc, char **argv)
> +{
> + uint32_t domid;
> + libxl_psr_type type;
> + uint64_t thrtl;
> + int ret, opt = 0;
> + libxl_bitmap target_map;
> + char *value;
> + libxl_string_list socket_list;
> + unsigned long start, end;
> + unsigned int i, j, len;
> +
> + static const struct option opts[] = {
> + {"socket", 1, 0, 's'},
> + COMMON_LONG_OPTS
> + };
> +
> + libxl_socket_bitmap_alloc(ctx, &target_map, 0);
> + libxl_bitmap_set_none(&target_map);
> +
> + SWITCH_FOREACH_OPT(opt, "s:", opts, "psr-mba-set", 0) {
> + case 's':
> + trim(isspace, optarg, &value);
> + split_string_into_string_list(value, ",", &socket_list);
> + len = libxl_string_list_length(&socket_list);
> + for (i = 0; i < len; i++) {
> + parse_range(socket_list[i], &start, &end);
Indentation.
> + for (j = start; j <= end; j++)
> + libxl_bitmap_set(&target_map, j);
> + }
> +
> + libxl_string_list_dispose(&socket_list);
> + free(value);
> + break;
> + }
> +
> + type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
> +
> + if (libxl_bitmap_is_empty(&target_map))
> + libxl_bitmap_set_any(&target_map);
> +
> + if (argc != optind + 2) {
> + help("psr-mba-set");
> + return 2;
> + }
Can you do this check at the beginning of the function? Also why
return 2 instead of EXIT_FAILURE?
Thanks, Roger.
_______________________________________________
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Xen-devel@lists.xen.org
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 15/15] docs: add MBA description in docs
2017-09-05 9:32 ` [PATCH v3 15/15] docs: add MBA description in docs Yi Sun
@ 2017-09-19 11:37 ` Roger Pau Monné
2017-09-20 7:26 ` Yi Sun
2017-09-28 16:56 ` Dario Faggioli
0 siblings, 2 replies; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-19 11:37 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Tue, Sep 05, 2017 at 05:32:37PM +0800, Yi Sun wrote:
> This patch adds MBA description in related documents.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> Acked-by: Wei Liu <wei.liu2@citrix.com>
> ---
> v2:
> - state the value type shown by 'psr-mba-show'. For linear mode,
> it shows decimal value. For non-linear mode, it shows hexadecimal
> value.
> (suggested by Chao Peng)
> ---
> docs/man/xl.pod.1.in | 34 +++++++++++++++++++++++++
> docs/misc/xl-psr.markdown | 63 +++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 97 insertions(+)
>
> diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
> index 16c8306..e644b19 100644
> --- a/docs/man/xl.pod.1.in
> +++ b/docs/man/xl.pod.1.in
> @@ -1798,6 +1798,40 @@ processed.
>
> =back
>
> +=head2 Memory Bandwidth Allocation
> +
> +Intel Skylake and later server platforms offer capabilities to configure and
> +make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
> +OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
I don't get the 'closed-loop' thing again, but that might just be me
since I'm not a native speaker.
> +control system via exposing control over a credit-based throttling mechanism.
> +In the Xen implementation, MBA is used to control memory bandwidth on VM basis.
> +To enforce bandwidth on a specific domain, just set throttling value (THRTL)
> +for the domain.
> +
> +=over 4
> +
> +=item B<psr-mba-set> [I<OPTIONS>] I<domain-id> I<thrtl>
> +
> +Set throttling value (THRTL) for a domain. For how to specify I<thrtl>
> +please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
> +
> +B<OPTIONS>
> +
> +=over 4
> +
> +=item B<-s SOCKET>, B<--socket=SOCKET>
> +
> +Specify the socket to process, otherwise all sockets are processed.
> +
> +=back
> +
> +=item B<psr-mba-show> [I<domain-id>]
> +
> +Show MBA settings for a certain domain or all domains. For linear mode, it
> +shows the decimal value. For non-linear mode, it shows hexadecimal value.
> +
> +=back
> +
> =head1 IGNORED FOR COMPATIBILITY WITH XM
>
> xl is mostly command-line compatible with the old xm utility used with
> diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
> index 04dd957..39fc801 100644
> --- a/docs/misc/xl-psr.markdown
> +++ b/docs/misc/xl-psr.markdown
> @@ -186,6 +186,69 @@ Setting data CBM for a domain:
> Setting the same code and data CBM for a domain:
> `xl psr-cat-set <domid> <cbm>`
>
> +## Memory Bandwidth Allocation (MBA)
> +
> +Memory Bandwidth Allocation (MBA) is a new feature available on Intel
> +Skylake and later server platforms that allows an OS or Hypervisor/VMM to
> +slow misbehaving apps/VMs or create advanced closed-loop control system via
> +exposing control over a credit-based throttling mechanism. To enforce bandwidth
> +on a specific domain, just set throttling value (THRTL) into Class of Service
> +(COS). MBA provides two THRTL mode. One is linear mode and the other is
> +non-linear mode.
> +
> +In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
> +not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
> +to 10% delay applied).
^ s/applied/by the hardware/
Thanks, Roger.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-19 6:07 ` Jan Beulich
@ 2017-09-20 2:59 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 2:59 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, chao.p.peng, xen-devel, dgdegra, roger.pau
On 17-09-19 00:07:36, Jan Beulich wrote:
> >>> Roger Pau Monné <roger.pau@citrix.com> 09/18/17 7:21 PM >>>
> >On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote:
> >> +## Hardware perspective
> >> +
> >> + MBA defines a range of MSRs to support specifying a delay value (Thrtl) per
> >> + COS, with details below.
> >> +
> >> + ```
> >> + +----------------------------+----------------+
> >> + | MSR (per socket) | Address |
> >> + +----------------------------+----------------+
> >> + | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
> >> + +----------------------------+----------------+
> >> + | ... | ... |
> >> + +----------------------------+----------------+
> >> + | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n |
> >> + +----------------------------+----------------+
> >> + ```
> >> +
> >> + When context switch happens, the COS ID of domain is written to per-thread MSR
> >> + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation according
> >
> >I think this is missing some context of the relation between a thread
> >and the MSR. I assume it's related to IA32_PQR_ASSOC, but I have no
> >idea what that constant means.
> >
> >What's more, Xen doesn't have threads, so you should maybe speak about
> >vCPUs instead?
>
> I think talk is of hardware aspects here, i.e. "thread" as in "hyper-thread".
>
> Jan
>
Indeed. Will make it more clear.
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> https://lists.xen.org/xen-devel
_______________________________________________
Xen-devel mailing list
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https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-18 17:16 ` Roger Pau Monné
2017-09-19 6:07 ` Jan Beulich
@ 2017-09-20 3:06 ` Yi Sun
2017-09-20 8:36 ` Roger Pau Monné
1 sibling, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-20 3:06 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-18 18:16:40, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote:
> > +* xl interfaces:
> > +
> > + 1. `psr-mba-show [domain-id]`:
>
> Is this limited to domain-id, or one can also use the domain name?
> Most of the xl commands accept either a domain-id or a domain-name.
>
Both domain-id and domain-name can show it. I thought this is by default and
no need to explicitly declare. If I am wrong, I will change it as below:
`psr-mba-show [domain-id/domain-name]`
[...]
> > + 2. `psr-mba-set [OPTIONS] <domain-id> <throttling>`:
> > +
> > + Set memory bandwidth throttling for domain.
> > +
> > + Options:
> > + '-s': Specify the socket to process, otherwise all sockets are processed.
> > +
> > + Throttling value set in register implies the approximate amount of delaying
> > + the traffic between core and memory. The higher throttling value results in
> > + lower bandwidth. The max throttling value (MBA_MAX) supported can be got
>
> s/got/obtained/
>
Thanks!
> > + through CPUID.
>
> How can one get this value empirically? Do I need to use a external
> tool?
>
Sorry for confusion. In fact, the MBA_MAX is got through CPUID in hypervisor.
User can know it through psr-hwinfo. Will explain it.
> > +
> > + Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
> > + if the MBA_MAX value is 90, the input precision is 10%. Values not an even
> > + multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
> > + delay applied) by HW automatically.
> > +
> > + Non-linear mode: input delay values are powers-of-two from zero to the
> > + MBA_MAX value from CPUID. In this case any values not a power of two will
> > + be rounded down the next nearest power of two by HW automatically.
>
> Both of the above descriptions should be moved to mba-show IMHO, the
> description there is incomplete and not helpful.
>
Ok, thanks!
> > +
> > +# Technical details
> > +
> > +MBA is a member of Intel PSR features, it shares the base PSR infrastructure
> > +in Xen.
> > +
> > +## Hardware perspective
> > +
> > + MBA defines a range of MSRs to support specifying a delay value (Thrtl) per
> > + COS, with details below.
> > +
> > + ```
> > + +----------------------------+----------------+
> > + | MSR (per socket) | Address |
> > + +----------------------------+----------------+
> > + | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
> > + +----------------------------+----------------+
> > + | ... | ... |
> > + +----------------------------+----------------+
> > + | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n |
> > + +----------------------------+----------------+
> > + ```
> > +
> > + When context switch happens, the COS ID of domain is written to per-thread MSR
> > + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation according
>
> I think this is missing some context of the relation between a thread
> and the MSR. I assume it's related to IA32_PQR_ASSOC, but I have no
> idea what that constant means.
>
> What's more, Xen doesn't have threads, so you should maybe speak about
> vCPUs instead?
>
As Jan's comment, this is for 'per-hyper-thread'.
[...]
> > +## Implementation Description
> > +
> > +* Hypervisor interfaces:
> > +
> > + 1. Boot line param: "psr=mba" to enable the feature.
> > +
> > + 2. SYSCTL:
> > + - XEN_SYSCTL_PSR_MBA_get_info: Get system MBA information.
>
> So this is likely how one gets the mentioned MBA_MAX?
>
Yup.
> > +
> > + 3. DOMCTL:
> > + - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get throttling for a domain.
> > + - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set throttling for a domain.
> > +
> > +* xl interfaces:
> > +
> > + 1. psr-mba-show [domain-id]
> > + Show system/domain runtime MBA throttling value. For linear mode,
> > + it shows the decimal value. For non-linear mode, it shows hexadecimal
> > + value.
> > + => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
> > +
> > + 2. psr-mba-set [OPTIONS] <domain-id> <throttling>
> > + Set bandwidth throttling for a domain.
> > + => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
> > +
> > + 3. psr-hwinfo
> > + Show PSR HW information, including L3 CAT/CDP/L2 CAT/MBA.
> > + => XEN_SYSCTL_PSR_MBA_get_info
>
> 'psr-hwinfo' seems to be completely missing from the 'xl interfaces:'
> section above.
>
Because this is not a newly added interface, I do not describe it in 'xl
interfaces'. Is that necessary?
> > +* Key data structure:
> > +
> > + 1. Feature HW info
> > +
> > + ```
> > + struct {
> > + unsigned int thrtl_max;
> > + bool linear;
> > + } mba;
> > +
> > + - Member `thrtl_max`
> > +
> > + `thrtl_max` is the max throttling value to be set, i.e. MBA_MAX.
> > +
> > + - Member `linear`
> > +
> > + `linear` means the response of delay value is linear or not.
> > +
> > + As mentioned above, MBA is a member of Intel PSR features, it would
> > + share the base PSR infrastructure in Xen. For example, the 'cos_max'
> > + is a common HW property for all features. So, for other data structure
> > + details, please refer 'intel_psr_cat_cdp.pandoc'.
> ^ to
Thanks!
> > +
> > +# Limitations
> > +
> > +MBA can only work on HW which enables it (check by CPUID).
> ^ s/enables/supports/.
Thanks!
> > +
> > +# Testing
> > +
> > +We can execute these commands to verify MBA on different HWs supporting them.
> > +
> > +For example:
> > + 1. User can get the MBA hardware info through 'psr-hwinfo' command. From
> > + result, user can know if this hardware works under linear mode or non-
> > + linear mode, the max throttling value (MBA_MAX) and so on.
> > +
> > + root@:~$ xl psr-hwinfo --mba
> > + Memory Bandwidth Allocation (MBA):
> > + Socket ID : 0
> > + Linear Mode : Enabled
> > + Maximum COS : 7
> > + Maximum Throttling Value: 90
> > + Default Throttling Value: 0
> > +
> > + 2. Then, user can set a throttling value to a domain. For example, set '0xa',
> > + i.e 10% delay.
> > +
> > + root@:~$ xl psr-mba-set 1 0xa
> > +
> > + 3. User can check the current configuration of the domain through
> > + 'psr-mab-show'. For linear mode, the decimal value is shown.
> > +
> > + root@:~$ xl psr-mba-show 1
> > + Socket ID : 0
> > + Default THRTL : 0
> > + ID NAME THRTL
> > + 1 ubuntu14 10
>
> The example seems better now IMHO.
>
> Thanks, Roger.
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-09-19 8:03 ` Roger Pau Monné
@ 2017-09-20 3:12 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 3:12 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 09:03:38, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:24PM +0800, Yi Sun wrote:
> > diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
> > index 0669c31..a953157 100644
> > --- a/xen/include/public/domctl.h
> > +++ b/xen/include/public/domctl.h
> > -struct xen_domctl_psr_cat_op {
> > -#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM 0
> > -#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM 1
> > -#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE 2
> > -#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA 3
> > -#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE 4
> > -#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
> > -#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
> > -#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
> > +struct xen_domctl_psr_alloc {
> > +#define XEN_DOMCTL_PSR_ALLOC_SET_L3_CBM 0
> > +#define XEN_DOMCTL_PSR_ALLOC_GET_L3_CBM 1
> > +#define XEN_DOMCTL_PSR_ALLOC_SET_L3_CODE 2
> > +#define XEN_DOMCTL_PSR_ALLOC_SET_L3_DATA 3
> > +#define XEN_DOMCTL_PSR_ALLOC_GET_L3_CODE 4
> > +#define XEN_DOMCTL_PSR_ALLOC_GET_L3_DATA 5
> > +#define XEN_DOMCTL_PSR_ALLOC_SET_L2_CBM 6
> > +#define XEN_DOMCTL_PSR_ALLOC_GET_L2_CBM 7
>
> IMHO, the _ALLOC_ part is not needed here, ALLOC_GET/SET seems quite
> weird to me, and redundant, since the type itself already contains
> _alloc).
Ok.
>
> > uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
>
> This comments needs fixing.
>
Yes, thanks!
[...]
> > diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
> > index 9e51af6..4759b10 100644
> > --- a/xen/include/public/sysctl.h
> > +++ b/xen/include/public/sysctl.h
> > @@ -36,7 +36,7 @@
> > #include "physdev.h"
> > #include "tmem.h"
> >
> > -#define XEN_SYSCTL_INTERFACE_VERSION 0x0000000F
> > +#define XEN_SYSCTL_INTERFACE_VERSION 0x00000010
> >
> > /*
> > * Read console content from Xen buffer ring.
> > @@ -743,22 +743,22 @@ struct xen_sysctl_pcitopoinfo {
> > typedef struct xen_sysctl_pcitopoinfo xen_sysctl_pcitopoinfo_t;
> > DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
> >
> > -#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
> > -#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
> > -struct xen_sysctl_psr_cat_op {
> > +#define XEN_SYSCTL_PSR_ALLOC_get_l3_info 0
> > +#define XEN_SYSCTL_PSR_ALLOC_get_l2_info 1
>
> Same here, I would drop the _ALLOC_.
>
Ok.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA
2017-09-19 8:55 ` Roger Pau Monné
@ 2017-09-20 3:22 ` Yi Sun
2017-09-20 7:11 ` Jan Beulich
0 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-20 3:22 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 09:55:28, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:26PM +0800, Yi Sun wrote:
> > This patch implements main data structures of MBA.
> >
> > Like CAT features, MBA HW info has cos_max which means the max thrtl
> > register number, and thrtl_max which means the max throttle value
> > (delay value). It also has a flag to represent if the throttle
> > value is linear or not.
> >
> > One thrtl register of MBA stores a throttle value for one or more
> > domains. The throttle value means the transaction time between L2
> > cache and next level memory to be delayed.
>
> "The throttle value contains the delay between L2 cache and the next
> cache level."
>
> Seems better, but I'm not a native speaker anyway.
>
Or:
"The throttle value means the delay between L2 cache and the next cache level."
[...]
> > struct feat_node {
> > - /* cos_max and cbm_len are common values for all features so far. */
> > + /* cos_max is common values for all features so far. */
>
> ...common among all features...
>
Ok, thanks!
[...]
> > +static int mba_init_feature(const struct cpuid_leaf *regs,
> > + struct feat_node *feat,
> > + struct psr_socket_info *info,
> > + enum psr_feat_type type)
> > +{
> > + /* No valid value so do not enable feature. */
> > + if ( !regs->a || !regs->d )
> > + return -ENOENT;
> > +
> > + if ( type != FEAT_TYPE_MBA )
> > + return -ENOENT;
>
> You can join the two checks above in a single if.
>
Sure.
> > +
> > + feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
> > + if ( feat->cos_max < 1 )
> > + return -ENOENT;
> > +
> > + feat->mba.thrtl_max = (regs->a & MBA_THRTL_MAX_MASK) + 1;
> > +
> > + if ( regs->c & MBA_LINEAR_MASK )
> > + {
> > + feat->mba.linear = true;
> > +
> > + if ( feat->mba.thrtl_max >= 100 )
> > + return -ENOENT;
> > + }
> > +
> > + /* We reserve cos=0 as default thrtl (0) which means no delay. */
> > + feat->cos_reg_val[0] = 0;
>
> AFAICT feat is allocated using xzalloc, so this will already be 0.
>
Yes, you are right. My original purpose is to explicitly let reader know that
'cos=0' is reserved. But the code is redundant that I will remove it.
> > @@ -1389,6 +1480,7 @@ static void psr_cpu_init(void)
> > unsigned int socket, cpu = smp_processor_id();
> > struct feat_node *feat;
> > struct cpuid_leaf regs;
> > + uint32_t reg_b;
>
> Not sure of the benefit between using regs.b or reg_b (it's only 1
> char shorter).
>
You can see the 'regs' is overwritten in below codes so that the 'regs.b' is not
kept. To add a new local variable 'reg_b' here, we can avoid calling
'cpuid_count_leaf' for L2 CAT and MBA.
> >
> > if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) )
> > goto assoc_init;
> > @@ -1407,7 +1499,8 @@ static void psr_cpu_init(void)
> > spin_lock_init(&info->ref_lock);
> >
> > cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
> > - if ( regs.b & PSR_RESOURCE_TYPE_L3 )
> > + reg_b = regs.b;
> > + if ( reg_b & PSR_RESOURCE_TYPE_L3 )
> > {
> > cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s);
> >
> > @@ -1428,8 +1521,7 @@ static void psr_cpu_init(void)
> > }
> > }
> >
> > - cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
> > - if ( regs.b & PSR_RESOURCE_TYPE_L2 )
> > + if ( reg_b & PSR_RESOURCE_TYPE_L2 )
> > {
> > cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);
> >
> > @@ -1441,6 +1533,18 @@ static void psr_cpu_init(void)
> > feat_l2_cat = feat;
> > }
> >
> > + if ( reg_b & PSR_RESOURCE_TYPE_MBA )
> > + {
> > + cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, ®s);
> > +
> > + feat = feat_mba;
> > + feat_mba = NULL;
> > + if ( !mba_init_feature(®s, feat, info, FEAT_TYPE_MBA) )
>
> Seems kind of pointless that mba_init_feature returns an error code
> when it's ignored by it's callers. You could switch it to bool if you
> are going to use it like that.
>
Hmm, bool type seems better. Thanks!
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 05/15] x86: implement get hw info flow for MBA
2017-09-19 9:08 ` Roger Pau Monné
@ 2017-09-20 5:05 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 5:05 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 10:08:22, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:27PM +0800, Yi Sun wrote:
> > diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> > index 10776d2..0486d2d 100644
> > --- a/xen/arch/x86/psr.c
> > +++ b/xen/arch/x86/psr.c
> > @@ -491,7 +495,18 @@ static const struct feat_props l2_cat_props = {
> > static bool mba_get_feat_info(const struct feat_node *feat,
> > uint32_t data[], unsigned int array_len)
> > {
> > - return false;
> > + if ( array_len != PSR_INFO_ARRAY_SIZE )
> > + return false;
> > +
> > + data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
> > + data[PSR_INFO_IDX_MBA_THRTL_MAX] = feat->mba.thrtl_max;
> > +
> > + if ( feat->mba.linear )
> > + data[PSR_INFO_IDX_MBA_FLAG] |= XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
> > + else
> > + data[PSR_INFO_IDX_MBA_FLAG] &= ~XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
>
> This branch of the if shouldn't be needed...
>
> > +
> > + return true;
> > }
> >
> > static void mba_write_msr(unsigned int cos, uint32_t val,
> > diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
> > index 1d3dbd0..4634cad 100644
> > --- a/xen/arch/x86/sysctl.c
> > +++ b/xen/arch/x86/sysctl.c
> > @@ -214,6 +214,25 @@ long arch_do_sysctl(
> > break;
> > }
> >
> > + case XEN_SYSCTL_PSR_ALLOC_get_mba_info:
> > + {
> > + ret = psr_get_info(sysctl->u.psr_alloc.target,
> > + PSR_TYPE_MBA_THRTL, data, ARRAY_SIZE(data));
>
> ... because data should be initialized, ie:
>
> uint32_t data[PSR_INFO_ARRAY_SIZE] = { 0 };
>
> So that we don't leak stack data in the sysctl.
>
Ok, thanks!
> Thanks, Roger.
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https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 06/15] x86: implement get value interface for MBA
2017-09-19 9:15 ` Roger Pau Monné
@ 2017-09-20 5:09 ` Yi Sun
2017-09-20 8:43 ` Roger Pau Monné
0 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-20 5:09 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 10:15:42, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:28PM +0800, Yi Sun wrote:
> > diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
> > index 696eff2..7902af7 100644
> > --- a/xen/arch/x86/domctl.c
> > +++ b/xen/arch/x86/domctl.c
> > @@ -1496,6 +1496,13 @@ long arch_do_domctl(
> > copyback = true;
> > break;
> >
> > + case XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL:
> > + ret = psr_get_val(d, domctl->u.psr_alloc.target,
> > + &val32, PSR_TYPE_MBA_THRTL);
> > + domctl->u.psr_alloc.data = val32;
>
> Hm, why does psr_get_val take a uint32_t * instead of a uint64_t *? So
> that you can directly pass &domctl->u.psr_alloc.data.
>
> Or the other way around, why is domctl->u.psr_alloc.data a uint64_t
> instead of a uint32_t?
>
There is a historical reason. The COS MSR is 64bit. So, the original codes
in L3 CAT (submitted years ago) used uint64_t.
But during L2 CAT review, per Jan's comment, the uint64_t is not necessary
in psr.c. So, we convert it to uint32_t in psr.c and make the codes you see
here.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 07/15] x86: implement set value flow for MBA
2017-09-19 9:57 ` Roger Pau Monné
@ 2017-09-20 5:39 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 5:39 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 10:57:16, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:29PM +0800, Yi Sun wrote:
[...]
> > +static bool cat_check_cbm(const struct feat_node *feat, unsigned long cbm)
> > +{
> > + unsigned int first_bit, zero_bit;
> > + unsigned int cbm_len = feat->cat.cbm_len;
> > +
> > + /* Set bits should only in the range of [0, cbm_len]. */
> > + if ( cbm & (~0ul << cbm_len) )
> > + return false;
> > +
> > + /* At least one bit need to be set. */
> > + if ( cbm == 0 )
> > + return false;
>
> You can join both checks into a single if.
>
Sure.
> > +
> > + first_bit = find_first_bit(&cbm, cbm_len);
> > + zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
> > +
> > + /* Set bits should be contiguous. */
> > + if ( zero_bit < cbm_len &&
> > + find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
> > + return false;
> > +
> > + return true;
> > +}
> > +
[...]
> > static void do_write_psr_msrs(void *data)
>
> Why does this function take a 'void *data' instead of 'const struct
> cos_write_info *info'?
>
Because 'do_write_psr_msrs' is an parameter of 'on_selected_cpus' which is
declared below:
void on_selected_cpus(
const cpumask_t *selected,
void (*func) (void *info),
void *info,
int wait)
> > {
> > const struct cos_write_info *info = data;
> > - struct feat_node *feat = info->feature;
> > - const struct feat_props *props = info->props;
> > - unsigned int i, cos = info->cos, cos_num = props->cos_num;
> > + unsigned int i, index = 0, array_len = info->array_len, cos = info->cos;
> > + const uint32_t *val_array = info->val;
> >
> > - for ( i = 0; i < cos_num; i++ )
> > + for ( i = 0; i < ARRAY_SIZE(feat_props); i++ )
> > {
> > - if ( feat->cos_reg_val[cos * cos_num + i] != info->val[i] )
> > + struct feat_node *feat = info->features[i];
> > + const struct feat_props *props = info->props[i];
> > + unsigned int cos_num, j;
> > +
> > + if ( !feat || !props )
> > + continue;
> > +
> > + cos_num = props->cos_num;
> > + if ( array_len < cos_num )
>
> Not sure you need array_len, couldn't you use:
>
> if ( index + cos_num >= info->array_len )
> return;
>
> ?
>
Looks good. Thanks!
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 08/15] tools: create general interfaces to support psr allocation features
2017-09-19 10:04 ` Roger Pau Monné
@ 2017-09-20 5:45 ` Yi Sun
2017-09-22 7:01 ` Chao Peng
1 sibling, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 5:45 UTC (permalink / raw)
Cc: xen-devel, roger.pau, ian.jackson, wei.liu2, chao.p.peng
Per Jan's suggestion, remove people not related to tools/ patches to save
mailbox space.
> On Tue, Sep 05, 2017 at 05:32:30PM +0800, Yi Sun wrote:
> > diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
> > index 484b5b7..9744087 100644
> > --- a/tools/libxl/libxl.h
> > +++ b/tools/libxl/libxl.h
> > @@ -931,6 +931,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src);
> > #define LIBXL_HAVE_PSR_L2_CAT 1
> >
> > /*
> > + * LIBXL_HAVE_PSR_GENERIC
> > + *
> > + * If this is defined, the Memory Bandwidth Allocation feature is supported.
>
> You should also mention that if this is defined the following public
> functions are available:
>
> libxl_psr_{set/get}_val
> libxl_psr_get_hw_info
> libxl_psr_hw_info_list_free
>
Sure, thanks!
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 09/15] tools: implement the new libxc get hw info interface
2017-09-19 10:15 ` Roger Pau Monné
@ 2017-09-20 6:13 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 6:13 UTC (permalink / raw)
Cc: xen-devel, roger.pau
On 17-09-19 11:15:11, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:31PM +0800, Yi Sun wrote:
> > diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
> > index c7710b8..bbdf8e2 100644
> > --- a/tools/libxc/include/xenctrl.h
> > +++ b/tools/libxc/include/xenctrl.h
> > @@ -2458,6 +2458,31 @@ enum xc_psr_cat_type {
> > };
> > typedef enum xc_psr_cat_type xc_psr_cat_type;
> >
> > +enum xc_psr_feat_type {
> > + XC_PSR_FEAT_UNKNOWN,
>
> You don't seem to have such an unknown type in the libxl layer, any
> reason you need it at the libxc layer?
>
It will be used in libxl_psr.c to check if libxl type convertion to libxc type
is correct.
But per your suggestion in libxl_psr.c, I may drop UNKNOWN.
> > + XC_PSR_FEAT_CAT_L3,
> > + XC_PSR_FEAT_CAT_L2,
> > + XC_PSR_FEAT_MBA,
>
> I think you can drop the _FEAT_ from the enum names.
>
Ok.
> > +};
> > +typedef enum xc_psr_feat_type xc_psr_feat_type;
> > +
> > +struct xc_psr_hw_info {
> > + union {
> > + struct {
> > + uint32_t cos_max;
> > + uint32_t cbm_len;
> > + bool cdp_enabled;
> > + } xc_cat;
>
> No need for the 'xc_cat', just 'cat' please (and 'mba' below).
>
Ok.
> > +
> > + struct {
> > + uint32_t cos_max;
> > + uint32_t thrtl_max;
> > + bool linear;
> > + } xc_mba;
> > + } u;
> > +};
> > +typedef struct xc_psr_hw_info xc_psr_hw_info;
> > +
[...]
> > -int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
> > - uint32_t *cos_max, uint32_t *cbm_len, bool *cdp_enabled)
> > +int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
> > + xc_psr_feat_type type, xc_psr_hw_info *hw_info)
> > {
[...]
> > + case XC_PSR_FEAT_MBA:
> > + sysctl.u.psr_alloc.cmd = XEN_SYSCTL_PSR_ALLOC_get_mba_info;
> > + rc = xc_sysctl(xch, &sysctl);
> > + if ( !rc )
> > + {
> > + hw_info->u.xc_mba.cos_max =
> > + sysctl.u.psr_alloc.u.mba_info.cos_max;
> > + hw_info->u.xc_mba.thrtl_max =
> > + sysctl.u.psr_alloc.u.mba_info.thrtl_max;
> > + hw_info->u.xc_mba.linear =
> > + sysctl.u.psr_alloc.u.mba_info.flags &
> > + XEN_SYSCTL_PSR_ALLOC_MBA_LINEAR;
> > }
>
> Would it help to prevent line breaks to change the indentation above
> to:
>
> rc = xc_sysctl(...);
> if ( rc )
> break;
>
> hw_info->u....
>
> ?
Let me try.
>
> > break;
> > default:
> > diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> > index 4a6978e..dd412cc 100644
> > --- a/tools/libxl/libxl_psr.c
> > +++ b/tools/libxl/libxl_psr.c
> > @@ -361,6 +361,27 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> > return rc;
> > }
> >
> > +static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
> > + libxl_psr_feat_type type, unsigned int lvl)
> > +{
> > + xc_psr_feat_type xc_type = XC_PSR_FEAT_UNKNOWN;
> > +
> > + switch (type) {
> > + case LIBXL_PSR_FEAT_TYPE_CAT:
> > + if (lvl == 3)
> > + xc_type = XC_PSR_FEAT_CAT_L3;
> > + if (lvl == 2)
> > + xc_type = XC_PSR_FEAT_CAT_L2;
> > + break;
> > + case LIBXL_PSR_FEAT_TYPE_MBA:
> > + xc_type = XC_PSR_FEAT_MBA;
> > + default:
> > + break;
>
> assert?
>
> libxl_psr_feat_type cannot have any other value apart from the two
> that you list above.
>
Ok, may consider it.
> > + }
> > +
> > + return xc_type;
> > +}
> > +
> > @@ -385,16 +408,27 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> > goto out;
> > }
> >
> > + xc_type = libxl__feat_type_to_libxc_feat_type(LIBXL_PSR_FEAT_TYPE_CAT, lvl);
> > + if (xc_type == XC_PSR_FEAT_UNKNOWN) {
> > + LOG(ERROR, "feature type or lvl is wrong");
> > + rc = ERROR_FAIL;
> > + goto out;
> > + }
> > +
> > ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
> >
> > libxl_for_each_set_bit(socketid, socketmap) {
> > ptr[i].id = socketid;
> > - if (xc_psr_cat_get_info(ctx->xch, socketid, lvl, &ptr[i].cos_max,
> > - &ptr[i].cbm_len, &ptr[i].cdp_enabled)) {
> > + if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
>
> It might be nice to LOG the errno here, or else you lose it AFAICT.
>
Ok.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 10/15] tools: implement the new libxl get hw info interface
2017-09-19 10:28 ` Roger Pau Monné
@ 2017-09-20 6:20 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 6:20 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 11:28:18, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:32PM +0800, Yi Sun wrote:
> > diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> > index dd412cc..d534ec2 100644
> > --- a/tools/libxl/libxl_psr.c
> > +++ b/tools/libxl/libxl_psr.c
> > @@ -382,60 +382,49 @@ static xc_psr_feat_type libxl__feat_type_to_libxc_feat_type(
> > return xc_type;
> > }
> >
> > +static int libxl__hw_info_to_libxl_cat_info(
> > + libxl_psr_feat_type type, libxl_psr_hw_info *hw_info,
> > + libxl_psr_cat_info *cat_info)
> > +{
> > + if (type != LIBXL_PSR_FEAT_TYPE_CAT)
> > + return ERROR_INVAL;
>
> Since this is an internal libxl function, is there any possible valid
> scenario where this function is called with type !=
> LIBXL_PSR_FEAT_TYPE_CAT?
>
> If not this should be an assert instead, and the function could return
> void.
>
Thanks for the good suggestion!
> > +
> > + cat_info->id = hw_info->id;
> > + cat_info->cos_max = hw_info->u.cat.cos_max;
> > + cat_info->cbm_len = hw_info->u.cat.cbm_len;
> > + cat_info->cdp_enabled = hw_info->u.cat.cdp_enabled;
> > +
> > + return 0;
> > +}
> > +
> > int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> > unsigned int *nr, unsigned int lvl)
> > {
[...]
> > - libxl_for_each_set_bit(socketid, socketmap) {
> > - ptr[i].id = socketid;
> > - if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
> > + for (i = 0; i < *nr; i++) {
> > + if (libxl__hw_info_to_libxl_cat_info(LIBXL_PSR_FEAT_TYPE_CAT,
> > + &hw_info[i], &ptr[i])) {
>
> Please use rc here:
>
> rc = libxl__hw_info_to_libxl_cat_info(...);
> if (rc) {
> ...
>
> This has the bonus of not losing the error code returned by
> libxl__hw_info_to_libxl_cat_info.
>
Ok.
> > + libxl_psr_hw_info_list_free(hw_info, *nr);
> > rc = ERROR_FAIL;
> > free(ptr);
> > goto out;
> > }
> > -
> > - ptr[i].cos_max = hw_info.u.xc_cat.cos_max;
> > - ptr[i].cbm_len = hw_info.u.xc_cat.cbm_len;
> > - ptr[i].cdp_enabled = hw_info.u.xc_cat.cdp_enabled;
> > -
> > - i++;
> > }
> >
> > *info = ptr;
> > - *nr = i;
> > + libxl_psr_hw_info_list_free(hw_info, *nr);
> > out:
> > - libxl_bitmap_dispose(&socketmap);
> > GC_FREE;
> > return rc;
> > }
> > @@ -476,15 +465,97 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
> > return ERROR_FAIL;
> > }
> >
[...]
> > void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr)
> > {
> > + unsigned int i;
> > +
> > + for (i = 0; i < nr; i++)
> > + libxl_psr_hw_info_dispose(&list[i]);
> > + free(list);
>
> Don't you also need a libxl_psr_cat_info_list_free? Or am I missing
> something?
>
The libxl_psr_cat_info_list_free is called in xl_psr.c which already exists in
original codes.
> > }
> >
> > /*
> > --
> > 1.9.1
> >
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 11/15] tools: implement the new xl get hw info interface
2017-09-19 10:32 ` Roger Pau Monné
@ 2017-09-20 6:23 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 6:23 UTC (permalink / raw)
To: Roger Pau Monn�; +Cc: xen-devel, ian.jackson, wei.liu2, chao.p.peng
On 17-09-19 11:32:19, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:33PM +0800, Yi Sun wrote:
> > index 6baaed2..a01245d 100644
> > --- a/tools/xl/xl_cmdtable.c
> > +++ b/tools/xl/xl_cmdtable.c
> > +static int psr_mba_hwinfo(void)
> > +{
> > + int rc;
> > + unsigned int i, nr;
> > + libxl_psr_hw_info *info;
> > +
> > + rc = libxl_psr_get_hw_info(ctx, &info, &nr,
> > + LIBXL_PSR_FEAT_TYPE_MBA, 0);
> > + if (rc)
> > + return rc;
> > +
> > + printf("Memory Bandwidth Allocation (MBA):\n");
> > +
> > + for (i = 0; i < nr; i++) {
> > + printf("Socket ID : %u\n", info[i].id);
> > + printf("Linear Mode : %s\n",
> > + info[i].u.mba.linear ? "Enabled" : "Disabled");
> > + printf("Maximum COS : %u\n", info[i].u.mba.cos_max);
> > + printf("Maximum Throttling Value: %u\n", info[i].u.mba.thrtl_max);
> > + printf("Default Throttling Value: %u\n", 0);
>
> What's the point in printing a default value if it's always 0? Ie:
> this can be on the docs, but I don't think is meaningful here.
>
This follows the convention of CAT. It shows the default CBM.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type'
2017-09-19 10:34 ` Roger Pau Monné
@ 2017-09-20 6:25 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 6:25 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 11:34:22, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:34PM +0800, Yi Sun wrote:
> > @@ -325,12 +325,12 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
> > }
> >
> > libxl_for_each_set_bit(socketid, *target_map) {
> > - xc_psr_cat_type xc_type;
> > + xc_psr_type xc_type;
> >
> > if (socketid >= nr_sockets)
> > break;
> >
> > - xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
> > + xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
>
> You can place this with the variable declaration:
>
> xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
>
Ok.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command
2017-09-19 11:02 ` Roger Pau Monné
@ 2017-09-20 6:46 ` Yi Sun
2017-09-20 8:57 ` Roger Pau Monné
0 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-20 6:46 UTC (permalink / raw)
To: Roger Pau Monn�; +Cc: xen-devel, ian.jackson, wei.liu2, chao.p.peng
On 17-09-19 12:02:08, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:35PM +0800, Yi Sun wrote:
> > diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
> > index c8d2921..78d5bc5 100644
> > --- a/tools/libxl/libxl_psr.c
> > +++ b/tools/libxl/libxl_psr.c
> > @@ -71,16 +71,30 @@ static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
> > LOGE(ERROR, "%s", msg);
> > }
> >
> > -static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> > +static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
> > + int err,
> > + libxl_psr_type type)
> > {
> > + /*
> > + * Index is 'libxl_psr_type' so we set two 'CDP' to correspond to
> > + * DATA and CODE.
> > + */
> > + const char * const feat_name[6] = {
>
> The explicit '6' is not needed.
>
> > + "UNKNOWN",
> > + "L3 CAT",
> > + "CDP",
> > + "CDP",
> > + "L2 CAT",
> > + "MBA",
>
> I'm not sure whether you want to use designated initializers here, in
> case someone decides to change the order of the xc_psr_type enum or
> the order here. ie:
>
> feat_name[]?= {
> [XC_PSR_CAT_L3_CBM] = "L3 CAT",
> [XC_PSR_CAT_L3_CBM_CODE..XC_PSR_CAT_L3_CBM_DATA] = "CDP",
> ...
> }
>
Got it. Thanks! One correction, the index is 'libxl_psr_type'.
> > + };
> > char *msg;
> >
> > switch (err) {
> > case ENODEV:
> > - msg = "CAT is not supported in this system";
> > + msg = "is not supported in this system";
> > break;
> > case ENOENT:
> > - msg = "CAT is not enabled on the socket";
> > + msg = "is not enabled on the socket";
> > break;
> > case EOVERFLOW:
> > msg = "no free COS available";
> > @@ -106,7 +120,7 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> > return;
> > }
> >
> > - LOGE(ERROR, "%s", msg);
> > + LOGE(ERROR, "%s: %s", feat_name[type], msg);
>
> I don't think you should use LOGE here, but rather LOG. LOGE should be
> used when errno is set, which I don't think is the case here.
>
But two places to call libxl__psr_cat_log_err_msg all set errno in 'xc_'
functions.
> > @@ -347,18 +361,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> > libxl_psr_cbm_type type, uint32_t target,
> > uint64_t *cbm_r)
> > {
> > - GC_INIT(ctx);
> > - int rc = 0;
> > - xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
> > -
> > - if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
> > - target, cbm_r)) {
> > - libxl__psr_cat_log_err_msg(gc, errno);
> > - rc = ERROR_FAIL;
> > - }
> > -
> > - GC_FREE;
> > - return rc;
> > + return libxl_psr_get_val(ctx, domid, type, target, cbm_r);
> > }
>
> You could even move this to libxl.h as a static function IMHO.
>
Yes. But I prefer to keep it here with other interfaces together. Is that
acceptable to you?
> > diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
> > index 40269b4..46b7788 100644
> > --- a/tools/xl/xl_psr.c
> > +++ b/tools/xl/xl_psr.c
> > -static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
> > - unsigned int lvl)
> > +static int psr_print_socket(uint32_t domid,
> > + libxl_psr_hw_info *info,
> > + libxl_psr_feat_type type,
> > + unsigned int lvl)
> > {
> > - int rc;
> > - uint32_t l3_cache_size;
> > -
> > printf("%-16s: %u\n", "Socket ID", info->id);
> >
> > - /* So far, CMT only supports L3 cache. */
> > - if (lvl == 3) {
> > - rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
> > - if (rc) {
> > - fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
> > - info->id);
> > - return -1;
> > + switch (type) {
> > + case LIBXL_PSR_FEAT_TYPE_CAT:
> > + {
> > + int rc;
> > + uint32_t l3_cache_size;
> > +
> > + /* So far, CMT only supports L3 cache. */
> > + if (lvl == 3) {
>
> Shouldn't you print some kind of error message if lvl != 3? Or is it
> expected that this function will be called with lvl != 3 and it should
> be ignored?
>
We only get cache size for level 3 cache. So, if input is lvl=2, we print
nothing.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA
2017-09-20 3:22 ` Yi Sun
@ 2017-09-20 7:11 ` Jan Beulich
2017-09-20 7:27 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Jan Beulich @ 2017-09-20 7:11 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, xen-devel, chao.p.peng, dgdegra,
Roger Pau Monn�
>>> On 20.09.17 at 05:22, <yi.y.sun@linux.intel.com> wrote:
> On 17-09-19 09:55:28, Roger Pau Monn wrote:
>> On Tue, Sep 05, 2017 at 05:32:26PM +0800, Yi Sun wrote:
>> > @@ -1389,6 +1480,7 @@ static void psr_cpu_init(void)
>> > unsigned int socket, cpu = smp_processor_id();
>> > struct feat_node *feat;
>> > struct cpuid_leaf regs;
>> > + uint32_t reg_b;
>>
>> Not sure of the benefit between using regs.b or reg_b (it's only 1
>> char shorter).
>>
> You can see the 'regs' is overwritten in below codes so that the 'regs.b' is not
> kept. To add a new local variable 'reg_b' here, we can avoid calling
> 'cpuid_count_leaf' for L2 CAT and MBA.
In which case - wouldn't "ebx" be a better name for the variable?
Jan
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 14/15] tools: implement new generic set value interface and MBA set value command
2017-09-19 11:30 ` Roger Pau Monné
@ 2017-09-20 7:25 ` Yi Sun
2017-09-20 16:10 ` Wei Liu
1 sibling, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 7:25 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-19 12:30:59, Roger Pau Monn� wrote:
> > int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> > @@ -458,7 +432,33 @@ int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
> > libxl_psr_type type, libxl_bitmap *target_map,
> > uint64_t val)
> > {
> > - return ERROR_FAIL;
> > + GC_INIT(ctx);
> > + int rc;
> > + int socketid, nr_sockets;
>
> You could fit them all in a single line.
>
Yes, thanks.
> > +int main_psr_mba_set(int argc, char **argv)
> > +{
> > + uint32_t domid;
> > + libxl_psr_type type;
> > + uint64_t thrtl;
> > + int ret, opt = 0;
> > + libxl_bitmap target_map;
> > + char *value;
> > + libxl_string_list socket_list;
> > + unsigned long start, end;
> > + unsigned int i, j, len;
> > +
> > + static const struct option opts[] = {
> > + {"socket", 1, 0, 's'},
> > + COMMON_LONG_OPTS
> > + };
> > +
> > + libxl_socket_bitmap_alloc(ctx, &target_map, 0);
> > + libxl_bitmap_set_none(&target_map);
> > +
> > + SWITCH_FOREACH_OPT(opt, "s:", opts, "psr-mba-set", 0) {
> > + case 's':
> > + trim(isspace, optarg, &value);
> > + split_string_into_string_list(value, ",", &socket_list);
> > + len = libxl_string_list_length(&socket_list);
> > + for (i = 0; i < len; i++) {
> > + parse_range(socket_list[i], &start, &end);
>
> Indentation.
>
Sorry.
> > + for (j = start; j <= end; j++)
> > + libxl_bitmap_set(&target_map, j);
> > + }
> > +
> > + libxl_string_list_dispose(&socket_list);
> > + free(value);
> > + break;
> > + }
> > +
> > + type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
> > +
> > + if (libxl_bitmap_is_empty(&target_map))
> > + libxl_bitmap_set_any(&target_map);
> > +
> > + if (argc != optind + 2) {
> > + help("psr-mba-set");
> > + return 2;
> > + }
>
> Can you do this check at the beginning of the function? Also why
> return 2 instead of EXIT_FAILURE?
>
Yes, will move it to the beginning. Will return EXIT_FAILURE.
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 15/15] docs: add MBA description in docs
2017-09-19 11:37 ` Roger Pau Monné
@ 2017-09-20 7:26 ` Yi Sun
2017-09-28 16:56 ` Dario Faggioli
1 sibling, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 7:26 UTC (permalink / raw)
To: Roger Pau Monn�; +Cc: xen-devel, ian.jackson, wei.liu2, chao.p.peng
On 17-09-19 12:37:24, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:37PM +0800, Yi Sun wrote:
> > +Intel Skylake and later server platforms offer capabilities to configure and
> > +make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
> > +OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
>
> I don't get the 'closed-loop' thing again, but that might just be me
> since I'm not a native speaker.
>
Will modify this to be same as feature doc.
[...]
> > +In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
> > +not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
> > +to 10% delay applied).
> ^ s/applied/by the hardware/
>
Thanks!
> Thanks, Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA
2017-09-20 7:11 ` Jan Beulich
@ 2017-09-20 7:27 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 7:27 UTC (permalink / raw)
To: Jan Beulich
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, chao.p.peng, xen-devel, dgdegra,
Roger Pau Monn�
On 17-09-20 01:11:50, Jan Beulich wrote:
> >>> On 20.09.17 at 05:22, <yi.y.sun@linux.intel.com> wrote:
> > On 17-09-19 09:55:28, Roger Pau Monn wrote:
> >> On Tue, Sep 05, 2017 at 05:32:26PM +0800, Yi Sun wrote:
> >> > @@ -1389,6 +1480,7 @@ static void psr_cpu_init(void)
> >> > unsigned int socket, cpu = smp_processor_id();
> >> > struct feat_node *feat;
> >> > struct cpuid_leaf regs;
> >> > + uint32_t reg_b;
> >>
> >> Not sure of the benefit between using regs.b or reg_b (it's only 1
> >> char shorter).
> >>
> > You can see the 'regs' is overwritten in below codes so that the 'regs.b' is not
> > kept. To add a new local variable 'reg_b' here, we can avoid calling
> > 'cpuid_count_leaf' for L2 CAT and MBA.
>
> In which case - wouldn't "ebx" be a better name for the variable?
>
Thanks for the suggestion!
> Jan
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> https://lists.xen.org/xen-devel
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-20 3:06 ` Yi Sun
@ 2017-09-20 8:36 ` Roger Pau Monné
2017-09-20 9:08 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-20 8:36 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Wed, Sep 20, 2017 at 11:06:57AM +0800, Yi Sun wrote:
> On 17-09-18 18:16:40, Roger Pau Monn� wrote:
> > On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote:
> > > +* xl interfaces:
> > > +
> > > + 1. `psr-mba-show [domain-id]`:
> >
> > Is this limited to domain-id, or one can also use the domain name?
> > Most of the xl commands accept either a domain-id or a domain-name.
> >
> Both domain-id and domain-name can show it. I thought this is by default and
> no need to explicitly declare. If I am wrong, I will change it as below:
> `psr-mba-show [domain-id/domain-name]`
[domain-id|domain-name]
Would be better IMHO.
> > > +
> > > + 3. DOMCTL:
> > > + - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get throttling for a domain.
> > > + - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set throttling for a domain.
> > > +
> > > +* xl interfaces:
> > > +
> > > + 1. psr-mba-show [domain-id]
> > > + Show system/domain runtime MBA throttling value. For linear mode,
> > > + it shows the decimal value. For non-linear mode, it shows hexadecimal
> > > + value.
> > > + => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
> > > +
> > > + 2. psr-mba-set [OPTIONS] <domain-id> <throttling>
> > > + Set bandwidth throttling for a domain.
> > > + => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
> > > +
> > > + 3. psr-hwinfo
> > > + Show PSR HW information, including L3 CAT/CDP/L2 CAT/MBA.
> > > + => XEN_SYSCTL_PSR_MBA_get_info
> >
> > 'psr-hwinfo' seems to be completely missing from the 'xl interfaces:'
> > section above.
> >
> Because this is not a newly added interface, I do not describe it in 'xl
> interfaces'. Is that necessary?
Oh, OK, sorry for the noise. Then I guess it's not necessary to
describe it here. Maybe a reference to where 'psr-hwinfo' is described
would be nice (I assume there's a feature document somewhere that
describes 'psr-hwinfo').
Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 06/15] x86: implement get value interface for MBA
2017-09-20 5:09 ` Yi Sun
@ 2017-09-20 8:43 ` Roger Pau Monné
2017-09-20 9:22 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-20 8:43 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On Wed, Sep 20, 2017 at 01:09:06PM +0800, Yi Sun wrote:
> On 17-09-19 10:15:42, Roger Pau Monn� wrote:
> > On Tue, Sep 05, 2017 at 05:32:28PM +0800, Yi Sun wrote:
> > > diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
> > > index 696eff2..7902af7 100644
> > > --- a/xen/arch/x86/domctl.c
> > > +++ b/xen/arch/x86/domctl.c
> > > @@ -1496,6 +1496,13 @@ long arch_do_domctl(
> > > copyback = true;
> > > break;
> > >
> > > + case XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL:
> > > + ret = psr_get_val(d, domctl->u.psr_alloc.target,
> > > + &val32, PSR_TYPE_MBA_THRTL);
> > > + domctl->u.psr_alloc.data = val32;
> >
> > Hm, why does psr_get_val take a uint32_t * instead of a uint64_t *? So
> > that you can directly pass &domctl->u.psr_alloc.data.
> >
> > Or the other way around, why is domctl->u.psr_alloc.data a uint64_t
> > instead of a uint32_t?
> >
> There is a historical reason. The COS MSR is 64bit. So, the original codes
> in L3 CAT (submitted years ago) used uint64_t.
>
> But during L2 CAT review, per Jan's comment, the uint64_t is not necessary
> in psr.c. So, we convert it to uint32_t in psr.c and make the codes you see
> here.
Since this is a DOMCTL, you can change the type of the structure to be
an uint32_t, so that you can pass it directly (unless I'm missing
something else that requires this to be uint64_t).
Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command
2017-09-20 6:46 ` Yi Sun
@ 2017-09-20 8:57 ` Roger Pau Monné
2017-09-20 9:11 ` Yi Sun
0 siblings, 1 reply; 62+ messages in thread
From: Roger Pau Monné @ 2017-09-20 8:57 UTC (permalink / raw)
To: Yi Sun; +Cc: xen-devel, ian.jackson, wei.liu2, chao.p.peng
On Wed, Sep 20, 2017 at 02:46:24PM +0800, Yi Sun wrote:
> On 17-09-19 12:02:08, Roger Pau Monn� wrote:
> > On Tue, Sep 05, 2017 at 05:32:35PM +0800, Yi Sun wrote:
> > > + };
> > > char *msg;
> > >
> > > switch (err) {
> > > case ENODEV:
> > > - msg = "CAT is not supported in this system";
> > > + msg = "is not supported in this system";
> > > break;
> > > case ENOENT:
> > > - msg = "CAT is not enabled on the socket";
> > > + msg = "is not enabled on the socket";
> > > break;
> > > case EOVERFLOW:
> > > msg = "no free COS available";
> > > @@ -106,7 +120,7 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> > > return;
> > > }
> > >
> > > - LOGE(ERROR, "%s", msg);
> > > + LOGE(ERROR, "%s: %s", feat_name[type], msg);
> >
> > I don't think you should use LOGE here, but rather LOG. LOGE should be
> > used when errno is set, which I don't think is the case here.
> >
> But two places to call libxl__psr_cat_log_err_msg all set errno in 'xc_'
> functions.
But you already translate the error into a custom message ('msg' in the
above context), and the error variable in this case is 'err' not
'errno', so LOGE is not appropriate here IMHO.
> > > @@ -347,18 +361,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
> > > libxl_psr_cbm_type type, uint32_t target,
> > > uint64_t *cbm_r)
> > > {
> > > - GC_INIT(ctx);
> > > - int rc = 0;
> > > - xc_psr_type xc_type = libxl__psr_cbm_type_to_libxc_psr_type(type);
> > > -
> > > - if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
> > > - target, cbm_r)) {
> > > - libxl__psr_cat_log_err_msg(gc, errno);
> > > - rc = ERROR_FAIL;
> > > - }
> > > -
> > > - GC_FREE;
> > > - return rc;
> > > + return libxl_psr_get_val(ctx, domid, type, target, cbm_r);
> > > }
> >
> > You could even move this to libxl.h as a static function IMHO.
> >
> Yes. But I prefer to keep it here with other interfaces together. Is that
> acceptable to you?
OK, as you wish.
> > > diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
> > > index 40269b4..46b7788 100644
> > > --- a/tools/xl/xl_psr.c
> > > +++ b/tools/xl/xl_psr.c
> > > -static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
> > > - unsigned int lvl)
> > > +static int psr_print_socket(uint32_t domid,
> > > + libxl_psr_hw_info *info,
> > > + libxl_psr_feat_type type,
> > > + unsigned int lvl)
> > > {
> > > - int rc;
> > > - uint32_t l3_cache_size;
> > > -
> > > printf("%-16s: %u\n", "Socket ID", info->id);
> > >
> > > - /* So far, CMT only supports L3 cache. */
> > > - if (lvl == 3) {
> > > - rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
> > > - if (rc) {
> > > - fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
> > > - info->id);
> > > - return -1;
> > > + switch (type) {
> > > + case LIBXL_PSR_FEAT_TYPE_CAT:
> > > + {
> > > + int rc;
> > > + uint32_t l3_cache_size;
> > > +
> > > + /* So far, CMT only supports L3 cache. */
> > > + if (lvl == 3) {
> >
> > Shouldn't you print some kind of error message if lvl != 3? Or is it
> > expected that this function will be called with lvl != 3 and it should
> > be ignored?
> >
> We only get cache size for level 3 cache. So, if input is lvl=2, we print
> nothing.
My question would be, is it expected that this function is called with
lvl == 2 as part of the normal operation with valid input values?
Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-09-20 8:36 ` Roger Pau Monné
@ 2017-09-20 9:08 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 9:08 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-20 09:36:13, Roger Pau Monn� wrote:
> On Wed, Sep 20, 2017 at 11:06:57AM +0800, Yi Sun wrote:
> > On 17-09-18 18:16:40, Roger Pau Monn� wrote:
> > > On Tue, Sep 05, 2017 at 05:32:23PM +0800, Yi Sun wrote:
> > > > +* xl interfaces:
> > > > +
> > > > + 1. `psr-mba-show [domain-id]`:
> > >
> > > Is this limited to domain-id, or one can also use the domain name?
> > > Most of the xl commands accept either a domain-id or a domain-name.
> > >
> > Both domain-id and domain-name can show it. I thought this is by default and
> > no need to explicitly declare. If I am wrong, I will change it as below:
> > `psr-mba-show [domain-id/domain-name]`
>
> [domain-id|domain-name]
>
> Would be better IMHO.
>
Thanks!
> > > > +
> > > > + 3. DOMCTL:
> > > > + - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get throttling for a domain.
> > > > + - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set throttling for a domain.
> > > > +
> > > > +* xl interfaces:
> > > > +
> > > > + 1. psr-mba-show [domain-id]
> > > > + Show system/domain runtime MBA throttling value. For linear mode,
> > > > + it shows the decimal value. For non-linear mode, it shows hexadecimal
> > > > + value.
> > > > + => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
> > > > +
> > > > + 2. psr-mba-set [OPTIONS] <domain-id> <throttling>
> > > > + Set bandwidth throttling for a domain.
> > > > + => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
> > > > +
> > > > + 3. psr-hwinfo
> > > > + Show PSR HW information, including L3 CAT/CDP/L2 CAT/MBA.
> > > > + => XEN_SYSCTL_PSR_MBA_get_info
> > >
> > > 'psr-hwinfo' seems to be completely missing from the 'xl interfaces:'
> > > section above.
> > >
> > Because this is not a newly added interface, I do not describe it in 'xl
> > interfaces'. Is that necessary?
>
> Oh, OK, sorry for the noise. Then I guess it's not necessary to
> describe it here. Maybe a reference to where 'psr-hwinfo' is described
> would be nice (I assume there's a feature document somewhere that
> describes 'psr-hwinfo').
>
psr-hwinfo is firstly introduced in intel_psr_cat_cdp.pandoc. But MBA feature
adds a new sysctl interface 'XEN_SYSCTL_PSR_MBA_get_info' which is used by
psr-hwinfo. So, I describe it here again.
> Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command
2017-09-20 8:57 ` Roger Pau Monné
@ 2017-09-20 9:11 ` Yi Sun
0 siblings, 0 replies; 62+ messages in thread
From: Yi Sun @ 2017-09-20 9:11 UTC (permalink / raw)
To: Roger Pau Monn�; +Cc: xen-devel, ian.jackson, wei.liu2, chao.p.peng
On 17-09-20 09:57:59, Roger Pau Monn� wrote:
> On Wed, Sep 20, 2017 at 02:46:24PM +0800, Yi Sun wrote:
> > On 17-09-19 12:02:08, Roger Pau Monn� wrote:
> > > On Tue, Sep 05, 2017 at 05:32:35PM +0800, Yi Sun wrote:
> > > > + };
> > > > char *msg;
> > > >
> > > > switch (err) {
> > > > case ENODEV:
> > > > - msg = "CAT is not supported in this system";
> > > > + msg = "is not supported in this system";
> > > > break;
> > > > case ENOENT:
> > > > - msg = "CAT is not enabled on the socket";
> > > > + msg = "is not enabled on the socket";
> > > > break;
> > > > case EOVERFLOW:
> > > > msg = "no free COS available";
> > > > @@ -106,7 +120,7 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> > > > return;
> > > > }
> > > >
> > > > - LOGE(ERROR, "%s", msg);
> > > > + LOGE(ERROR, "%s: %s", feat_name[type], msg);
> > >
> > > I don't think you should use LOGE here, but rather LOG. LOGE should be
> > > used when errno is set, which I don't think is the case here.
> > >
> > But two places to call libxl__psr_cat_log_err_msg all set errno in 'xc_'
> > functions.
>
> But you already translate the error into a custom message ('msg' in the
> above context), and the error variable in this case is 'err' not
> 'errno', so LOGE is not appropriate here IMHO.
>
Ok.
[...]
> > > > diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
> > > > index 40269b4..46b7788 100644
> > > > --- a/tools/xl/xl_psr.c
> > > > +++ b/tools/xl/xl_psr.c
> > > > -static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
> > > > - unsigned int lvl)
> > > > +static int psr_print_socket(uint32_t domid,
> > > > + libxl_psr_hw_info *info,
> > > > + libxl_psr_feat_type type,
> > > > + unsigned int lvl)
> > > > {
> > > > - int rc;
> > > > - uint32_t l3_cache_size;
> > > > -
> > > > printf("%-16s: %u\n", "Socket ID", info->id);
> > > >
> > > > - /* So far, CMT only supports L3 cache. */
> > > > - if (lvl == 3) {
> > > > - rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
> > > > - if (rc) {
> > > > - fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
> > > > - info->id);
> > > > - return -1;
> > > > + switch (type) {
> > > > + case LIBXL_PSR_FEAT_TYPE_CAT:
> > > > + {
> > > > + int rc;
> > > > + uint32_t l3_cache_size;
> > > > +
> > > > + /* So far, CMT only supports L3 cache. */
> > > > + if (lvl == 3) {
> > >
> > > Shouldn't you print some kind of error message if lvl != 3? Or is it
> > > expected that this function will be called with lvl != 3 and it should
> > > be ignored?
> > >
> > We only get cache size for level 3 cache. So, if input is lvl=2, we print
> > nothing.
>
> My question would be, is it expected that this function is called with
> lvl == 2 as part of the normal operation with valid input values?
>
Yes, lvl == 2 is a normal operation.
> Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 06/15] x86: implement get value interface for MBA
2017-09-20 8:43 ` Roger Pau Monné
@ 2017-09-20 9:22 ` Yi Sun
2017-09-20 16:02 ` Wei Liu
0 siblings, 1 reply; 62+ messages in thread
From: Yi Sun @ 2017-09-20 9:22 UTC (permalink / raw)
To: Roger Pau Monn�
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra
On 17-09-20 09:43:40, Roger Pau Monn� wrote:
> On Wed, Sep 20, 2017 at 01:09:06PM +0800, Yi Sun wrote:
> > On 17-09-19 10:15:42, Roger Pau Monn� wrote:
> > > On Tue, Sep 05, 2017 at 05:32:28PM +0800, Yi Sun wrote:
> > > > diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
> > > > index 696eff2..7902af7 100644
> > > > --- a/xen/arch/x86/domctl.c
> > > > +++ b/xen/arch/x86/domctl.c
> > > > @@ -1496,6 +1496,13 @@ long arch_do_domctl(
> > > > copyback = true;
> > > > break;
> > > >
> > > > + case XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL:
> > > > + ret = psr_get_val(d, domctl->u.psr_alloc.target,
> > > > + &val32, PSR_TYPE_MBA_THRTL);
> > > > + domctl->u.psr_alloc.data = val32;
> > >
> > > Hm, why does psr_get_val take a uint32_t * instead of a uint64_t *? So
> > > that you can directly pass &domctl->u.psr_alloc.data.
> > >
> > > Or the other way around, why is domctl->u.psr_alloc.data a uint64_t
> > > instead of a uint32_t?
> > >
> > There is a historical reason. The COS MSR is 64bit. So, the original codes
> > in L3 CAT (submitted years ago) used uint64_t.
> >
> > But during L2 CAT review, per Jan's comment, the uint64_t is not necessary
> > in psr.c. So, we convert it to uint32_t in psr.c and make the codes you see
> > here.
>
> Since this is a DOMCTL, you can change the type of the structure to be
> an uint32_t, so that you can pass it directly (unless I'm missing
> something else that requires this to be uint64_t).
>
The tools layer implementation uses uint64_t according to SDM definition. So,
we have to do a convertion here or in tools/. Or, we need modify interfaces in
tools layer.
As CAT interfaces in tools layer have been released and it is a natural choice
to make it same as SDM, I think should keep uint64_t in tools at least. If so,
we must do the convertion somewhere. Then, I think it is not so necessary to
change current codes. Is that good to you?
> Roger.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 06/15] x86: implement get value interface for MBA
2017-09-20 9:22 ` Yi Sun
@ 2017-09-20 16:02 ` Wei Liu
0 siblings, 0 replies; 62+ messages in thread
From: Wei Liu @ 2017-09-20 16:02 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel, dgdegra,
Roger Pau Monn�
On Wed, Sep 20, 2017 at 05:22:22PM +0800, Yi Sun wrote:
> On 17-09-20 09:43:40, Roger Pau Monn� wrote:
> > On Wed, Sep 20, 2017 at 01:09:06PM +0800, Yi Sun wrote:
> > > On 17-09-19 10:15:42, Roger Pau Monn� wrote:
> > > > On Tue, Sep 05, 2017 at 05:32:28PM +0800, Yi Sun wrote:
> > > > > diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
> > > > > index 696eff2..7902af7 100644
> > > > > --- a/xen/arch/x86/domctl.c
> > > > > +++ b/xen/arch/x86/domctl.c
> > > > > @@ -1496,6 +1496,13 @@ long arch_do_domctl(
> > > > > copyback = true;
> > > > > break;
> > > > >
> > > > > + case XEN_DOMCTL_PSR_ALLOC_GET_MBA_THRTL:
> > > > > + ret = psr_get_val(d, domctl->u.psr_alloc.target,
> > > > > + &val32, PSR_TYPE_MBA_THRTL);
> > > > > + domctl->u.psr_alloc.data = val32;
> > > >
> > > > Hm, why does psr_get_val take a uint32_t * instead of a uint64_t *? So
> > > > that you can directly pass &domctl->u.psr_alloc.data.
> > > >
> > > > Or the other way around, why is domctl->u.psr_alloc.data a uint64_t
> > > > instead of a uint32_t?
> > > >
> > > There is a historical reason. The COS MSR is 64bit. So, the original codes
> > > in L3 CAT (submitted years ago) used uint64_t.
> > >
> > > But during L2 CAT review, per Jan's comment, the uint64_t is not necessary
> > > in psr.c. So, we convert it to uint32_t in psr.c and make the codes you see
> > > here.
> >
> > Since this is a DOMCTL, you can change the type of the structure to be
> > an uint32_t, so that you can pass it directly (unless I'm missing
> > something else that requires this to be uint64_t).
> >
> The tools layer implementation uses uint64_t according to SDM definition. So,
> we have to do a convertion here or in tools/. Or, we need modify interfaces in
> tools layer.
>
> As CAT interfaces in tools layer have been released and it is a natural choice
> to make it same as SDM, I think should keep uint64_t in tools at least. If so,
> we must do the convertion somewhere. Then, I think it is not so necessary to
> change current codes. Is that good to you?
You can change libxc interfaces at will, you need to pay more attention
if you change libxl. This is just FYI. I'm not suggesting you have to
change the interfaces.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 14/15] tools: implement new generic set value interface and MBA set value command
2017-09-19 11:30 ` Roger Pau Monné
2017-09-20 7:25 ` Yi Sun
@ 2017-09-20 16:10 ` Wei Liu
2017-09-28 16:23 ` Dario Faggioli
1 sibling, 1 reply; 62+ messages in thread
From: Wei Liu @ 2017-09-20 16:10 UTC (permalink / raw)
To: Roger Pau Monné
Cc: wei.liu2, kevin.tian, Yi Sun, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, dgdegra
On Tue, Sep 19, 2017 at 12:30:59PM +0100, Roger Pau Monné wrote:
> > + type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
> > +
> > + if (libxl_bitmap_is_empty(&target_map))
> > + libxl_bitmap_set_any(&target_map);
> > +
> > + if (argc != optind + 2) {
> > + help("psr-mba-set");
> > + return 2;
> > + }
>
> Can you do this check at the beginning of the function? Also why
> return 2 instead of EXIT_FAILURE?
>
Returning 2 is used in several places when help string is printed. It
isn't really consistent in xl though.
I'm not too fussed whether it is 2 or EXIT_FAILURE.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 08/15] tools: create general interfaces to support psr allocation features
2017-09-19 10:04 ` Roger Pau Monné
2017-09-20 5:45 ` Yi Sun
@ 2017-09-22 7:01 ` Chao Peng
2017-09-28 16:11 ` Wei Liu
1 sibling, 1 reply; 62+ messages in thread
From: Chao Peng @ 2017-09-22 7:01 UTC (permalink / raw)
To: Roger Pau Monné, Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, xen-devel, dgdegra
On Tue, 2017-09-19 at 11:04 +0100, Roger Pau Monné wrote:
> On Tue, Sep 05, 2017 at 05:32:30PM +0800, Yi Sun wrote:
> >
> > This patch creates general interfaces in libxl to support all psr
> > allocation features.
> >
> > Add 'LIBXL_HAVE_PSR_GENERIC' to indicate interface change.
> >
> > Please note, the functionality cannot work until later patches
> > are applied.
> >
> > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> > ---
> > v3:
> > - change 'LIBXL_HAVE_PSR_MBA' to 'LIBXL_HAVE_PSR_GENERIC'.
> > (suggested by Roger Pau Monné)
> > - 'typedef enum libxl_psr_cbm_type libxl_psr_type;' in libxl.h.
> > (suggested by Roger Pau Monné and Wei Liu)
> > - change 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly
> > defined
> > interfaces.
> > (suggested by Roger Pau Monné)
> > v2:
> > - remove '_INFO' in 'libxl_psr_feat_type' and make corresponding
> > changes in 'libxl_psr_hw_info'.
> > (suggested by Chao Peng)
> > ---
> > tools/libxl/libxl.h | 33 +++++++++++++++++++++++++++++++++
> > tools/libxl/libxl_psr.c | 25 +++++++++++++++++++++++++
> > tools/libxl/libxl_types.idl | 22 ++++++++++++++++++++++
> > 3 files changed, 80 insertions(+)
> >
> > diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
> > index 484b5b7..9744087 100644
> > --- a/tools/libxl/libxl.h
> > +++ b/tools/libxl/libxl.h
> > @@ -931,6 +931,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac
> > *dst, const libxl_mac *src);
> > #define LIBXL_HAVE_PSR_L2_CAT 1
> >
> > /*
> > + * LIBXL_HAVE_PSR_GENERIC
> > + *
> > + * If this is defined, the Memory Bandwidth Allocation feature is
> > supported.
>
> You should also mention that if this is defined the following public
> functions are available:
>
> libxl_psr_{set/get}_val
> libxl_psr_get_hw_info
> libxl_psr_hw_info_list_free
>
I'm just wondering what macro we will use when more PSR generic routines
are needed in the future releases. LIBXL_HAVE_PSR_GENERIC2?
Thanks,
Chao
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 08/15] tools: create general interfaces to support psr allocation features
2017-09-22 7:01 ` Chao Peng
@ 2017-09-28 16:11 ` Wei Liu
0 siblings, 0 replies; 62+ messages in thread
From: Wei Liu @ 2017-09-28 16:11 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, xen-devel, Yi Sun, dgdegra,
Roger Pau Monné
On Fri, Sep 22, 2017 at 03:01:42PM +0800, Chao Peng wrote:
> On Tue, 2017-09-19 at 11:04 +0100, Roger Pau Monné wrote:
> > On Tue, Sep 05, 2017 at 05:32:30PM +0800, Yi Sun wrote:
> > >
> > > This patch creates general interfaces in libxl to support all psr
> > > allocation features.
> > >
> > > Add 'LIBXL_HAVE_PSR_GENERIC' to indicate interface change.
> > >
> > > Please note, the functionality cannot work until later patches
> > > are applied.
> > >
> > > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> > > ---
> > > v3:
> > > - change 'LIBXL_HAVE_PSR_MBA' to 'LIBXL_HAVE_PSR_GENERIC'.
> > > (suggested by Roger Pau Monné)
> > > - 'typedef enum libxl_psr_cbm_type libxl_psr_type;' in libxl.h.
> > > (suggested by Roger Pau Monné and Wei Liu)
> > > - change 'libxl_psr_cbm_type' to 'libxl_psr_type' in newly
> > > defined
> > > interfaces.
> > > (suggested by Roger Pau Monné)
> > > v2:
> > > - remove '_INFO' in 'libxl_psr_feat_type' and make corresponding
> > > changes in 'libxl_psr_hw_info'.
> > > (suggested by Chao Peng)
> > > ---
> > > tools/libxl/libxl.h | 33 +++++++++++++++++++++++++++++++++
> > > tools/libxl/libxl_psr.c | 25 +++++++++++++++++++++++++
> > > tools/libxl/libxl_types.idl | 22 ++++++++++++++++++++++
> > > 3 files changed, 80 insertions(+)
> > >
> > > diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
> > > index 484b5b7..9744087 100644
> > > --- a/tools/libxl/libxl.h
> > > +++ b/tools/libxl/libxl.h
> > > @@ -931,6 +931,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac
> > > *dst, const libxl_mac *src);
> > > #define LIBXL_HAVE_PSR_L2_CAT 1
> > >
> > > /*
> > > + * LIBXL_HAVE_PSR_GENERIC
> > > + *
> > > + * If this is defined, the Memory Bandwidth Allocation feature is
> > > supported.
> >
> > You should also mention that if this is defined the following public
> > functions are available:
> >
> > libxl_psr_{set/get}_val
> > libxl_psr_get_hw_info
> > libxl_psr_hw_info_list_free
> >
>
> I'm just wondering what macro we will use when more PSR generic routines
> are needed in the future releases. LIBXL_HAVE_PSR_GENERIC2?
GENERIC2 sounds horrible but if we have to, so be it. But I suppose we
can always think of better names. We shall cross the bridge when we gets
there.
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 14/15] tools: implement new generic set value interface and MBA set value command
2017-09-20 16:10 ` Wei Liu
@ 2017-09-28 16:23 ` Dario Faggioli
2017-09-29 12:58 ` Wei Liu
0 siblings, 1 reply; 62+ messages in thread
From: Dario Faggioli @ 2017-09-28 16:23 UTC (permalink / raw)
To: Wei Liu, Roger Pau Monné
Cc: kevin.tian, Yi Sun, andrew.cooper3, ian.jackson, julien.grall,
mengxu, jbeulich, xen-devel, chao.p.peng, dgdegra
[-- Attachment #1.1: Type: text/plain, Size: 1565 bytes --]
On Wed, 2017-09-20 at 17:10 +0100, Wei Liu wrote:
> On Tue, Sep 19, 2017 at 12:30:59PM +0100, Roger Pau Monné wrote:
> > > + type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
> > > +
> > > + if (libxl_bitmap_is_empty(&target_map))
> > > + libxl_bitmap_set_any(&target_map);
> > > +
> > > + if (argc != optind + 2) {
> > > + help("psr-mba-set");
> > > + return 2;
> > > + }
> >
> > Can you do this check at the beginning of the function? Also why
> > return 2 instead of EXIT_FAILURE?
> >
>
> Returning 2 is used in several places when help string is
> printed. It
> isn't really consistent in xl though.
>
True. However, there's been efforts for improving that (consistency, I
mean) and getting to a situation where only EXIT_SUCCESS or
EXIT_FAILURE are used.
I know it's not a done deal yet, and that it's being a slow process,
but I think it would be nice if new code would help achieving that,
instead than making it more difficult. :-)
Then...
> I'm not too fussed whether it is 2 or EXIT_FAILURE.
>
...this is just my opinion (as one of the ones which was part of that
effort, and that plans to get back to finish it at some point). You're
the maintainer, your rules. :-P :-D
Regards,
Dario
--
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 15/15] docs: add MBA description in docs
2017-09-19 11:37 ` Roger Pau Monné
2017-09-20 7:26 ` Yi Sun
@ 2017-09-28 16:56 ` Dario Faggioli
1 sibling, 0 replies; 62+ messages in thread
From: Dario Faggioli @ 2017-09-28 16:56 UTC (permalink / raw)
To: Roger Pau Monné, Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, ian.jackson, julien.grall,
mengxu, jbeulich, xen-devel, chao.p.peng, dgdegra
[-- Attachment #1.1: Type: text/plain, Size: 3252 bytes --]
On Tue, 2017-09-19 at 12:37 +0100, Roger Pau Monné wrote:
> On Tue, Sep 05, 2017 at 05:32:37PM +0800, Yi Sun wrote:
> >
> > --- a/docs/man/xl.pod.1.in
> > +++ b/docs/man/xl.pod.1.in
> > @@ -1798,6 +1798,40 @@ processed.
> >
> > =back
> >
> > +=head2 Memory Bandwidth Allocation
> > +
> > +Intel Skylake and later server platforms offer capabilities to
> > configure and
> > +make use of the Memory Bandwidth Allocation (MBA) mechanisms,
> > which provides
> > +OS/VMMs the ability to slow misbehaving apps/VMs or create
> > advanced closed-loop
>
> I don't get the 'closed-loop' thing again, but that might just be me
> since I'm not a native speaker.
>
> > +control system via exposing control over a credit-based throttling
> > mechanism.
>
It goes together with 'control system'. In fact, 'closed-loop control
system' is a concept from control theory (or system automation, or
system theory... I've head it called in all these ways).
It's when you want to control a system, or a process, and you do it by
enclosing it in a "loop" in such a way that the n+1-th input to the
process is influenced by the n-th output of the process itself. It's
also called 'feedback-loop' or 'feedback-based control system'.
Basically, you usually read/measure/sense the n-th output of the
process, you compare it with some 'desired' value, and you use --as the
process' n+1-th input-- some indication of how different the measured
value was from the desired value.
http://www.electronics-tutorials.ws/systems/closed-loop-system.html
Alternatively, you have 'open-loop control systems', where there is no
sensing of the output, and no feedback mechanism that would correct the
input according to how things are actually going (i.e., someone says,
there is no control!).
http://www.electronics-tutorials.ws/systems/open-loop-system.html
*I guess* what this means, in this context, is that, with both MBA and
MBM, you can build a piece of software that, given a desired memory
bandwidth usage, for a certain domain, sets MBA accordingly, then
monitors what the domain is actually getting, and use the difference
between that and the desired value to drive the new value to be set,
using MBA again. Like, if it's getting less, give it _some_ more, if
it's getting more, give it _some_ less (where both the _some_-s are
coefficients).
Ideally, after initial spikes and fluctuations (which depends on the
coefficients, and on which one can do math, still using control theory
concepts), happening, e.g., when the workload inside the VM changes,
the bandwidth utilization will settle at the desired point.
All that being said, I'd say that either more details are given (or a
link is put here, pointing to a whitepaper or in general a place where
a full description of the solution can be found), or it's probably
better to drop the 'close-loop' reference, and explain how MBA can be
useful in another way.
Regards,
Dario
--
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
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^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v3 14/15] tools: implement new generic set value interface and MBA set value command
2017-09-28 16:23 ` Dario Faggioli
@ 2017-09-29 12:58 ` Wei Liu
0 siblings, 0 replies; 62+ messages in thread
From: Wei Liu @ 2017-09-29 12:58 UTC (permalink / raw)
To: Dario Faggioli
Cc: kevin.tian, Yi Sun, xen-devel, andrew.cooper3, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, Wei Liu, dgdegra,
Roger Pau Monné
On Thu, Sep 28, 2017 at 06:23:16PM +0200, Dario Faggioli wrote:
> On Wed, 2017-09-20 at 17:10 +0100, Wei Liu wrote:
> > On Tue, Sep 19, 2017 at 12:30:59PM +0100, Roger Pau Monné wrote:
> > > > + type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
> > > > +
> > > > + if (libxl_bitmap_is_empty(&target_map))
> > > > + libxl_bitmap_set_any(&target_map);
> > > > +
> > > > + if (argc != optind + 2) {
> > > > + help("psr-mba-set");
> > > > + return 2;
> > > > + }
> > >
> > > Can you do this check at the beginning of the function? Also why
> > > return 2 instead of EXIT_FAILURE?
> > >
> >
> > Returning 2 is used in several places when help string is
> > printed. It
> > isn't really consistent in xl though.
> >
> True. However, there's been efforts for improving that (consistency, I
> mean) and getting to a situation where only EXIT_SUCCESS or
> EXIT_FAILURE are used.
>
> I know it's not a done deal yet, and that it's being a slow process,
> but I think it would be nice if new code would help achieving that,
> instead than making it more difficult. :-)
>
> Then...
>
> > I'm not too fussed whether it is 2 or EXIT_FAILURE.
> >
> ...this is just my opinion (as one of the ones which was part of that
> effort, and that plans to get back to finish it at some point). You're
> the maintainer, your rules. :-P :-D
>
This makes sense.
If Yi doesn't end up changing it to EXIT_FAILURE, I will do that myself.
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^ permalink raw reply [flat|nested] 62+ messages in thread
end of thread, other threads:[~2017-09-29 12:59 UTC | newest]
Thread overview: 62+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-09-05 9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-09-05 9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-09-18 17:16 ` Roger Pau Monné
2017-09-19 6:07 ` Jan Beulich
2017-09-20 2:59 ` Yi Sun
2017-09-20 3:06 ` Yi Sun
2017-09-20 8:36 ` Roger Pau Monné
2017-09-20 9:08 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-09-19 8:03 ` Roger Pau Monné
2017-09-20 3:12 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
2017-09-19 8:22 ` Roger Pau Monné
2017-09-05 9:32 ` [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-09-19 8:55 ` Roger Pau Monné
2017-09-20 3:22 ` Yi Sun
2017-09-20 7:11 ` Jan Beulich
2017-09-20 7:27 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 05/15] x86: implement get hw info " Yi Sun
2017-09-19 9:08 ` Roger Pau Monné
2017-09-20 5:05 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 06/15] x86: implement get value interface " Yi Sun
2017-09-19 9:15 ` Roger Pau Monné
2017-09-20 5:09 ` Yi Sun
2017-09-20 8:43 ` Roger Pau Monné
2017-09-20 9:22 ` Yi Sun
2017-09-20 16:02 ` Wei Liu
2017-09-05 9:32 ` [PATCH v3 07/15] x86: implement set value flow " Yi Sun
2017-09-19 9:57 ` Roger Pau Monné
2017-09-20 5:39 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 08/15] tools: create general interfaces to support psr allocation features Yi Sun
2017-09-19 10:04 ` Roger Pau Monné
2017-09-20 5:45 ` Yi Sun
2017-09-22 7:01 ` Chao Peng
2017-09-28 16:11 ` Wei Liu
2017-09-05 9:32 ` [PATCH v3 09/15] tools: implement the new libxc get hw info interface Yi Sun
2017-09-19 10:15 ` Roger Pau Monné
2017-09-20 6:13 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 10/15] tools: implement the new libxl " Yi Sun
2017-09-19 10:28 ` Roger Pau Monné
2017-09-20 6:20 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 11/15] tools: implement the new xl " Yi Sun
2017-09-19 10:32 ` Roger Pau Monné
2017-09-20 6:23 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
2017-09-19 10:34 ` Roger Pau Monné
2017-09-20 6:25 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command Yi Sun
2017-09-19 11:02 ` Roger Pau Monné
2017-09-20 6:46 ` Yi Sun
2017-09-20 8:57 ` Roger Pau Monné
2017-09-20 9:11 ` Yi Sun
2017-09-05 9:32 ` [PATCH v3 14/15] tools: implement new generic set value interface and MBA set " Yi Sun
2017-09-19 11:30 ` Roger Pau Monné
2017-09-20 7:25 ` Yi Sun
2017-09-20 16:10 ` Wei Liu
2017-09-28 16:23 ` Dario Faggioli
2017-09-29 12:58 ` Wei Liu
2017-09-05 9:32 ` [PATCH v3 15/15] docs: add MBA description in docs Yi Sun
2017-09-19 11:37 ` Roger Pau Monné
2017-09-20 7:26 ` Yi Sun
2017-09-28 16:56 ` Dario Faggioli
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