From: Yi Sun <yi.y.sun@linux.intel.com>
To: xen-devel@lists.xenproject.org
Cc: "Wei Liu" <wei.liu2@citrix.com>,
"Yi Sun" <yi.y.sun@linux.intel.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Chao Peng" <chao.p.peng@linux.intel.com>,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH v5 08/16] x86: implement set value flow for MBA
Date: Sat, 30 Sep 2017 09:39:18 +0800 [thread overview]
Message-ID: <1506735566-5706-9-git-send-email-yi.y.sun@linux.intel.com> (raw)
In-Reply-To: <1506735566-5706-1-git-send-email-yi.y.sun@linux.intel.com>
This patch implements set value flow for MBA including its callback
function and domctl interface.
It also changes the memebers in 'cos_write_info' to transfer the
feature array, feature properties array and value array. Then, we
can write all features values on the cos id into MSRs.
Because multiple features may co-exist, we need handle all features to write
values of them into a COS register with new COS ID. E.g:
1. L3 CAT and MBA co-exist.
2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of Dom1 is 0x1ff,
the MBA Thrtle of Dom1 is 0xa.
3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because COS ID 2 is
used by Dom2 too, we have to pick a new COS ID 3. The values of Dom1 on
COS ID 3 are all default values as below:
---------
| COS 3 |
---------
L3 CAT | 0x7ff |
---------
MBA | 0x0 |
---------
4. After setting, the L3 CAT CBM value of Dom1 should be kept and the new MBA
Thrtl is set. So, the values on COS ID 3 should be below.
---------
| COS 3 |
---------
L3 CAT | 0x1ff |
---------
MBA | 0x14 |
---------
So, we should write all features values into their MSRs. That requires the
feature array, feature properties array and value array are input.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
CC: Jan Beulich <jbeulich@suse.com>
CC: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Wei Liu <wei.liu2@citrix.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
CC: Chao Peng <chao.p.peng@linux.intel.com>
v5:
- adjust position of 'cat_check_cbm' to not to make changes so big.
(suggested by Roger Pau Monné)
- remove 'props' from 'struct cos_write_info'.
(suggested by Roger Pau Monné)
- make a single return statement in 'mba_check_thrtl'.
(suggested by Jan Beulich)
v4:
- remove 'ALLOC_' from macro names.
(suggested by Roger Pau Monné)
- join two checks into a single if.
(suggested by Roger Pau Monné)
- remove redundant local variable 'array_len'.
(suggested by Roger Pau Monné)
v3:
- modify commit message to make it clear.
(suggested by Roger Pau Monné)
- modify functionality of 'check_val' to make it simple to only check value.
Change the last parameter type from 'unsigned long *' to 'unsigned long'.
(suggested by Roger Pau Monné)
- call rdmsrl to get value just written into MSR for MBA. Because HW can
automatically change input value to what it wants.
(suggested by Roger Pau Monné)
- change type of 'write_msr' to 'uint32_t' to return the value actually
written into MSR. Then, change 'do_write_psr_msrs' to set the returned
value into 'cos_reg_val[]'
- move the declaration of 'j' into loop in 'do_write_psr_msrs'.
(suggested by Roger Pau Monné)
- change 'mba_info' to 'mba'.
(suggested by Roger Pau Monné)
- change 'cat_info' to 'cat'.
(suggested by Roger Pau Monné)
- rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
from name.
(suggested by Roger Pau Monné)
- change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
v2:
- remove linear mode 'thrtl_max' check in 'mba_check_thrtl' because it has
been checked in 'mba_init_feature'.
(suggested by Chao Peng)
- for non-linear mode, check if '*thrtl' is not 0 in 'mba_check_thrtl'. If
it is 0, we do not need to change it.
(suggested by Chao Peng)
- move comments to explain changes of 'cos_write_info' from psr.c to commit
message.
(suggested by Chao Peng)
---
xen/arch/x86/domctl.c | 6 ++++
xen/arch/x86/psr.c | 86 +++++++++++++++++++++++++++------------------
xen/include/public/domctl.h | 1 +
3 files changed, 59 insertions(+), 34 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 5fb443f..e5f6a24 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1476,6 +1476,12 @@ long arch_do_domctl(
PSR_TYPE_L2_CBM);
break;
+ case XEN_DOMCTL_PSR_SET_MBA_THRTL:
+ ret = psr_set_val(d, domctl->u.psr_alloc.target,
+ domctl->u.psr_alloc.data,
+ PSR_TYPE_MBA_THRTL);
+ break;
+
case XEN_DOMCTL_PSR_GET_L3_CBM:
ret = domctl_psr_get_val(d, domctl, PSR_TYPE_L3_CBM, copyback);
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 66e20a7..32e5122 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -138,6 +138,9 @@ static const struct feat_props {
/* write_msr is used to write out feature MSR register. */
uint32_t (*write_msr)(unsigned int cos, uint32_t val, enum psr_type type);
+
+ /* check_val is used to check if input val fulfills SDM requirement. */
+ bool (*check_val)(const struct feat_node *feat, unsigned long val);
} *feat_props[FEAT_TYPE_NUM];
/*
@@ -274,16 +277,17 @@ static enum psr_feat_type psr_type_to_feat_type(enum psr_type type)
return feat_type;
}
-static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
+/* Implementation of allocation features' functions. */
+static bool cat_check_cbm(const struct feat_node *feat, unsigned long cbm)
{
unsigned int first_bit, zero_bit;
+ unsigned int cbm_len = feat->cat.cbm_len;
- /* Set bits should only in the range of [0, cbm_len]. */
- if ( cbm & (~0ul << cbm_len) )
- return false;
-
- /* At least one bit need to be set. */
- if ( cbm == 0 )
+ /*
+ * Set bits should only in the range of [0, cbm_len].
+ * And, at least one bit need to be set.
+ */
+ if ( cbm & (~0ul << cbm_len) || cbm == 0 )
return false;
first_bit = find_first_bit(&cbm, cbm_len);
@@ -297,7 +301,6 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
return true;
}
-/* Implementation of allocation features' functions. */
static bool cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
struct psr_socket_info *info,
@@ -438,6 +441,7 @@ static const struct feat_props l3_cat_props = {
.alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l3_cat_write_msr,
+ .check_val = cat_check_cbm,
};
/* L3 CDP props */
@@ -470,6 +474,7 @@ static const struct feat_props l3_cdp_props = {
.alt_type = PSR_TYPE_L3_CBM,
.get_feat_info = l3_cdp_get_feat_info,
.write_msr = l3_cdp_write_msr,
+ .check_val = cat_check_cbm,
};
/* L2 CAT props */
@@ -487,6 +492,7 @@ static const struct feat_props l2_cat_props = {
.alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l2_cat_write_msr,
+ .check_val = cat_check_cbm,
};
/* MBA props */
@@ -507,7 +513,17 @@ static bool mba_get_feat_info(const struct feat_node *feat,
static uint32_t mba_write_msr(unsigned int cos, uint32_t val,
enum psr_type type)
{
- return 0;
+ wrmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
+
+ /* Read actual value set by hardware. */
+ rdmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
+
+ return val;
+}
+
+static bool mba_check_thrtl(const struct feat_node *feat, unsigned long thrtl)
+{
+ return ( thrtl > feat->mba.thrtl_max ) ? false : true;
}
static const struct feat_props mba_props = {
@@ -516,6 +532,7 @@ static const struct feat_props mba_props = {
.alt_type = PSR_TYPE_UNKNOWN,
.get_feat_info = mba_get_feat_info,
.write_msr = mba_write_msr,
+ .check_val = mba_check_thrtl,
};
static bool __init parse_psr_bool(const char *s, const char *delim,
@@ -981,7 +998,7 @@ static int insert_val_into_array(uint32_t val[],
if ( array_len < props->cos_num )
return -ENOSPC;
- if ( !psr_check_cbm(feat->cat.cbm_len, new_val) )
+ if ( !props->check_val(feat, new_val) )
return -EINVAL;
/*
@@ -1213,25 +1230,38 @@ static unsigned int get_socket_cpu(unsigned int socket)
struct cos_write_info
{
unsigned int cos;
- struct feat_node *feature;
+ struct feat_node **features;
const uint32_t *val;
- const struct feat_props *props;
+ unsigned int array_len;
};
static void do_write_psr_msrs(void *data)
{
const struct cos_write_info *info = data;
- struct feat_node *feat = info->feature;
- const struct feat_props *props = info->props;
- unsigned int i, cos = info->cos, cos_num = props->cos_num;
+ unsigned int i, index = 0, cos = info->cos;
+ const uint32_t *val_array = info->val;
- for ( i = 0; i < cos_num; i++ )
+ for ( i = 0; i < ARRAY_SIZE(feat_props); i++ )
{
- if ( feat->cos_reg_val[cos * cos_num + i] != info->val[i] )
+ struct feat_node *feat = info->features[i];
+ const struct feat_props *props = feat_props[i];
+ unsigned int cos_num, j;
+
+ if ( !feat || !props )
+ continue;
+
+ cos_num = props->cos_num;
+ if ( info->array_len < index + cos_num )
+ return;
+
+ for ( j = 0; j < cos_num; j++ )
{
- feat->cos_reg_val[cos * cos_num + i] = info->val[i];
- props->write_msr(cos, info->val[i], props->type[i]);
+ if ( feat->cos_reg_val[cos * cos_num + j] != val_array[index + j] )
+ feat->cos_reg_val[cos * cos_num + j] =
+ props->write_msr(cos, val_array[index + j], props->type[j]);
}
+
+ index += cos_num;
}
}
@@ -1239,30 +1269,18 @@ static int write_psr_msrs(unsigned int socket, unsigned int cos,
const uint32_t val[], unsigned int array_len,
enum psr_feat_type feat_type)
{
- int ret;
struct psr_socket_info *info = get_socket_info(socket);
struct cos_write_info data =
{
.cos = cos,
- .feature = info->features[feat_type],
- .props = feat_props[feat_type],
+ .features = info->features,
+ .val = val,
+ .array_len = array_len,
};
if ( cos > info->features[feat_type]->cos_max )
return -EINVAL;
- /* Skip to the feature's value head. */
- ret = skip_prior_features(&array_len, feat_type);
- if ( ret < 0 )
- return ret;
-
- val += ret;
-
- if ( array_len < feat_props[feat_type]->cos_num )
- return -ENOSPC;
-
- data.val = val;
-
if ( socket == cpu_to_socket(smp_processor_id()) )
do_write_psr_msrs(&data);
else
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 1231d37..19d20d0 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1156,6 +1156,7 @@ struct xen_domctl_psr_alloc {
#define XEN_DOMCTL_PSR_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_SET_MBA_THRTL 8
#define XEN_DOMCTL_PSR_GET_MBA_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_* */
uint32_t target; /* IN */
--
1.9.1
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next prev parent reply other threads:[~2017-09-30 1:59 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-30 1:39 [PATCH v5 00/16] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-09-30 1:39 ` [PATCH v5 01/16] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-10-06 14:59 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 02/16] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-10-05 11:36 ` Wei Liu
2017-10-06 16:53 ` Roger Pau Monné
2017-10-09 8:12 ` Jan Beulich
2017-09-30 1:39 ` [PATCH v5 03/16] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
2017-09-30 1:39 ` [PATCH v5 04/16] x86: a few optimizations to psr codes Yi Sun
2017-10-06 16:59 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 05/16] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-10-06 17:13 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 06/16] x86: implement get hw info " Yi Sun
2017-10-06 17:16 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 07/16] x86: implement get value interface " Yi Sun
2017-09-30 1:39 ` Yi Sun [this message]
2017-10-06 17:18 ` [PATCH v5 08/16] x86: implement set value flow " Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 09/16] tools: create general interfaces to support psr allocation features Yi Sun
2017-10-05 11:31 ` Wei Liu
2017-10-06 17:20 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 10/16] tools: implement the new libxc get hw info interface Yi Sun
2017-10-05 11:31 ` Wei Liu
2017-10-06 17:25 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 11/16] tools: implement the new libxl " Yi Sun
2017-10-05 11:31 ` Wei Liu
2017-09-30 1:39 ` [PATCH v5 12/16] tools: implement the new xl " Yi Sun
2017-10-05 11:31 ` Wei Liu
2017-09-30 1:39 ` [PATCH v5 13/16] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
2017-09-30 1:39 ` [PATCH v5 14/16] tools: implement new generic get value interface and MBA get value command Yi Sun
2017-10-06 17:30 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 15/16] tools: implement new generic set value interface and MBA set " Yi Sun
2017-10-05 11:31 ` Wei Liu
2017-10-06 17:33 ` Roger Pau Monné
2017-09-30 1:39 ` [PATCH v5 16/16] docs: add MBA description in docs Yi Sun
2017-10-05 11:27 ` [PATCH v5 00/16] Enable Memory Bandwidth Allocation in Xen Wei Liu
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