From: Yang Zhong <yang.zhong@intel.com>
To: xen-devel@lists.xen.org
Cc: yang.zhong@intel.com, yi.y.sun@intel.com, chao.p.peng@intel.com,
luwei.kang@intel.com, yu.c.zhang@intel.com
Subject: [PATCH v2 2/4] x86emul: Support GFNI insns
Date: Fri, 10 Nov 2017 17:36:06 +0800 [thread overview]
Message-ID: <1510306568-9701-3-git-send-email-yang.zhong@intel.com> (raw)
In-Reply-To: <1510306568-9701-1-git-send-email-yang.zhong@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
xen/arch/x86/x86_emulate/x86_emulate.c | 22 ++++++++++++++++++++++
xen/include/asm-x86/cpufeature.h | 3 +++
2 files changed, 25 insertions(+)
diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emulate/x86_emulate.c
index 54a2756..c207f61 100644
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -385,6 +385,7 @@ static const struct {
[0x40] = { .simd_size = simd_packed_int },
[0x41] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xc8 ... 0xcd] = { .simd_size = simd_other },
+ [0xcf] = { .simd_size = simd_other },
[0xdb] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xdc ... 0xdf] = { .simd_size = simd_packed_int },
[0xf0] = { .two_op = 1 },
@@ -421,6 +422,7 @@ static const struct {
[0x4c] = { .simd_size = simd_packed_int, .four_op = 1 },
[0x60 ... 0x63] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xcc] = { .simd_size = simd_other },
+ [0xce ... 0xcf] = { .simd_size = simd_other },
[0xdf] = { .simd_size = simd_packed_int, .two_op = 1 },
[0xf0] = {},
};
@@ -1623,6 +1625,7 @@ static bool vcpu_has(
#define vcpu_has_clflushopt() vcpu_has( 7, EBX, 23, ctxt, ops)
#define vcpu_has_clwb() vcpu_has( 7, EBX, 24, ctxt, ops)
#define vcpu_has_sha() vcpu_has( 7, EBX, 29, ctxt, ops)
+#define vcpu_has_gfni() vcpu_has( 7, ECX, 8, ctxt, ops)
#define vcpu_has_rdpid() vcpu_has( 7, ECX, 22, ctxt, ops)
#define vcpu_has_clzero() vcpu_has(0x80000008, EBX, 0, ctxt, ops)
@@ -7356,6 +7359,14 @@ x86_emulate(
op_bytes = 16;
goto simd_0f38_common;
+ case X86EMUL_OPC_66(0x0f38, 0xcf): /* gf2p8mulb xmm/m128,xmm*/
+ case X86EMUL_OPC_VEX_66(0x0f38, 0xcf): /* vgf2p8mulb xmm/m128,xmm*/
+ host_and_vcpu_must_have(gfni);
+ if ( vex.opcx == vex_none )
+ goto simd_0f38_common;
+ else
+ goto simd_0f_avx;
+
case X86EMUL_OPC(0x0f38, 0xf0): /* movbe m,r */
case X86EMUL_OPC(0x0f38, 0xf1): /* movbe r,m */
vcpu_must_have(movbe);
@@ -7741,6 +7752,17 @@ x86_emulate(
op_bytes = 16;
goto simd_0f3a_common;
+ case X86EMUL_OPC_66(0x0f3a, 0xce): /* gf2p8affineqb $imm8,xmm/m128,xmm*/
+ case X86EMUL_OPC_VEX_66(0x0f3a, 0xce): /* vgf2p8affineqb $imm8,xmm/m128,xmm*/
+ case X86EMUL_OPC_66(0x0f3a, 0xcf): /* gf2p8affineinvqb $imm8,xmm/m128,xmm*/
+ case X86EMUL_OPC_VEX_66(0x0f3a, 0xcf): /* vgf2p8affineinvqb $imm8,xmm/m128,xmm*/
+ host_and_vcpu_must_have(gfni);
+ if ( vex.opcx == vex_none )
+ goto simd_0f3a_common;
+ else
+ goto simd_0f_imm8_avx;
+
+
case X86EMUL_OPC_66(0x0f3a, 0xdf): /* aeskeygenassist $imm8,xmm/m128,xmm */
case X86EMUL_OPC_VEX_66(0x0f3a, 0xdf): /* vaeskeygenassist $imm8,xmm/m128,xmm */
host_and_vcpu_must_have(aesni);
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 84cc51d..9c43cd8 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -97,6 +97,9 @@
#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
+/* CPUID level 0x00000007:0.ecx */
+#define cpu_has_gfni boot_cpu_has(X86_FEATURE_GFNI)
+
/* CPUID level 0x80000007.edx */
#define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC)
--
1.9.1
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next prev parent reply other threads:[~2017-11-10 9:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-10 9:36 [PATCH v2 0/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features Yang Zhong
2017-11-10 9:36 ` [PATCH v2 1/4] " Yang Zhong
2017-11-10 10:32 ` Jan Beulich
2017-11-10 10:43 ` Zhong Yang
2017-11-10 9:36 ` Yang Zhong [this message]
2017-11-10 9:36 ` [PATCH v2 3/4] x86emul: Support vpclmulqdq Yang Zhong
2017-11-10 9:36 ` [PATCH v2 4/4] x86emul: Support vaes insns Yang Zhong
2017-11-10 9:42 ` [PATCH v2 0/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features Jan Beulich
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