From: Luwei Kang <luwei.kang@intel.com>
To: xen-devel@lists.xen.org
Cc: kevin.tian@intel.com, sstabellini@kernel.org,
wei.liu2@citrix.com, jbeulich@suse.com,
George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com,
tim@xen.org, jun.nakajima@intel.com,
Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH RESEND v1 4/7] x86: add intel processor trace context
Date: Tue, 16 Jan 2018 02:12:30 +0800 [thread overview]
Message-ID: <1516039953-2988-5-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1516039953-2988-1-git-send-email-luwei.kang@intel.com>
This patch add Intel processor trace context
date structure for guest.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
xen/include/asm-x86/hvm/vmx/vmcs.h | 3 +++
xen/include/asm-x86/intel_pt.h | 17 +++++++++++++++++
xen/include/asm-x86/msr-index.h | 20 ++++++++++++++++++++
3 files changed, 40 insertions(+)
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index bd8a128..33ec3e6 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -20,6 +20,7 @@
#include <asm/hvm/io.h>
#include <irq_vectors.h>
+#include <asm/intel_pt.h>
extern void vmcs_dump_vcpu(struct vcpu *v);
extern void setup_vmcs_dump(void);
@@ -171,6 +172,8 @@ struct arch_vmx_struct {
* pCPU and wakeup the related vCPU.
*/
struct pi_blocking_vcpu pi_blocking;
+
+ struct pt_desc pt_desc;
};
int vmx_create_vmcs(struct vcpu *v);
diff --git a/xen/include/asm-x86/intel_pt.h b/xen/include/asm-x86/intel_pt.h
index 2a8b579..909e22f 100644
--- a/xen/include/asm-x86/intel_pt.h
+++ b/xen/include/asm-x86/intel_pt.h
@@ -21,6 +21,23 @@
#ifndef __ASM_X86_HVM_INTEL_PT_H_
#define __ASM_X86_HVM_INTEL_PT_H_
+#include <asm/msr-index.h>
+
+struct pt_ctx {
+ u64 ctl;
+ u64 status;
+ u64 output_base;
+ u64 output_mask;
+ u64 cr3_match;
+ u64 addr[NUM_MSR_IA32_RTIT_ADDR];
+};
+
+struct pt_desc {
+ bool intel_pt_enabled;
+ unsigned int addr_num;
+ struct pt_ctx guest_pt_ctx;
+};
+
extern bool_t opt_intel_pt;
#endif /* __ASM_X86_HVM_INTEL_PT_H_ */
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index a834f3b..73c33be 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -529,4 +529,24 @@
#define MSR_PKGC9_IRTL 0x00000634
#define MSR_PKGC10_IRTL 0x00000635
+/* Intel PT MSRs */
+#define MSR_IA32_RTIT_CTL 0x00000570
+#define _MSR_IA32_RTIT_CTL_TRACEEN 0
+#define MSR_IA32_RTIT_CTL_TRACEEN (1ULL << _MSR_IA32_RTIT_CTL_TRACEEN)
+#define _MSR_IA32_RTIT_CTL_TOPA 8
+#define MSR_IA32_RTIT_CTL_TOPA (1ULL << _MSR_IA32_RTIT_CTL_TOPA)
+#define MSR_IA32_RTIT_STATUS 0x00000571
+#define MSR_IA32_RTIT_CR3_MATCH 0x00000572
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
+#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561
+#define MSR_IA32_RTIT_ADDR0_A 0x00000580
+#define MSR_IA32_RTIT_ADDR0_B 0x00000581
+#define MSR_IA32_RTIT_ADDR1_A 0x00000582
+#define MSR_IA32_RTIT_ADDR1_B 0x00000583
+#define MSR_IA32_RTIT_ADDR2_A 0x00000584
+#define MSR_IA32_RTIT_ADDR2_B 0x00000585
+#define MSR_IA32_RTIT_ADDR3_A 0x00000586
+#define MSR_IA32_RTIT_ADDR3_B 0x00000587
+#define NUM_MSR_IA32_RTIT_ADDR 8
+
#endif /* __ASM_MSR_INDEX_H */
--
1.8.3.1
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next prev parent reply other threads:[~2018-01-15 18:12 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-15 18:12 [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling Luwei Kang
2018-01-15 18:12 ` [PATCH RESEND v1 1/7] x86: add a flag to enable Intel processor trace Luwei Kang
2018-03-09 16:53 ` Wei Liu
2018-03-12 9:25 ` Kang, Luwei
2018-04-26 12:09 ` Wei Liu
2018-04-27 8:22 ` Kang, Luwei
2018-04-27 8:32 ` Wei Liu
2018-04-27 13:03 ` Jan Beulich
2018-04-27 23:16 ` Kang, Luwei
2018-04-26 12:29 ` Jan Beulich
2018-04-27 9:01 ` Kang, Luwei
2018-04-27 12:15 ` Jan Beulich
2018-04-27 23:18 ` Kang, Luwei
2018-01-15 18:12 ` [PATCH RESEND v1 2/7] x86: configure vmcs for Intel processor trace virtualization Luwei Kang
2018-04-26 12:34 ` Jan Beulich
2018-04-28 1:07 ` Kang, Luwei
2018-04-30 7:42 ` Jan Beulich
2018-05-02 7:22 ` Kang, Luwei
2018-05-02 9:09 ` Jan Beulich
2018-05-02 9:22 ` Kang, Luwei
2018-01-15 18:12 ` [PATCH RESEND v1 3/7] x86: add intel proecessor trace support for cpuid Luwei Kang
2018-04-30 15:43 ` Konrad Rzeszutek Wilk
2018-05-02 7:32 ` Kang, Luwei
2018-01-15 18:12 ` Luwei Kang [this message]
2018-04-26 12:11 ` [PATCH RESEND v1 4/7] x86: add intel processor trace context Wei Liu
2018-04-26 12:59 ` Jan Beulich
2018-04-28 1:26 ` Kang, Luwei
2018-01-15 18:12 ` [PATCH RESEND v1 5/7] x86: Implement Intel Processor Trace context switch Luwei Kang
2018-04-26 12:11 ` Wei Liu
2018-04-27 8:53 ` Kang, Luwei
2018-05-02 15:19 ` Wei Liu
2018-05-02 15:43 ` Jan Beulich
2018-05-02 16:15 ` Wei Liu
2018-05-02 16:51 ` Andrew Cooper
2018-05-03 7:27 ` Jan Beulich
2018-05-03 7:26 ` Jan Beulich
2018-05-03 7:51 ` Wei Liu
2018-04-26 13:12 ` Jan Beulich
2018-04-28 2:56 ` Kang, Luwei
2018-01-15 18:12 ` [PATCH RESEND v1 6/7] x86: Implement Intel Processor Trace MSRs read/write Luwei Kang
2018-04-26 13:20 ` Jan Beulich
2018-04-27 12:26 ` Jan Beulich
2018-05-03 5:22 ` Kang, Luwei
2018-05-03 7:33 ` Jan Beulich
2018-05-03 9:40 ` Kang, Luwei
2018-05-03 11:36 ` Jan Beulich
2018-05-04 3:53 ` Kang, Luwei
2018-05-04 12:06 ` Jan Beulich
2018-05-10 9:06 ` Kang, Luwei
2018-01-15 18:12 ` [PATCH RESEND v1 7/7] x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-01-16 8:41 ` [PATCH RESEND v1 0/7] Intel Processor Trace virtulization enabling Jan Beulich
2018-01-16 9:02 ` Kang, Luwei
2018-01-16 9:30 ` Jan Beulich
2018-01-16 9:45 ` Kang, Luwei
2018-04-26 12:12 ` Wei Liu
2018-05-03 4:06 ` Kang, Luwei
2018-05-03 5:55 ` Razvan Cojocaru
2018-05-03 8:06 ` Wei Liu
2018-05-04 4:10 ` Kang, Luwei
2018-05-03 9:49 ` Kang, Luwei
2018-05-03 10:01 ` Andrew Cooper
2018-05-04 3:08 ` Kang, Luwei
2018-05-10 9:26 ` Kang, Luwei
2018-05-10 9:56 ` Andrew Cooper
2018-05-15 2:50 ` Kang, Luwei
2018-04-30 15:42 ` Konrad Rzeszutek Wilk
2018-05-02 7:27 ` Kang, Luwei
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