[PATCH v2 09/10] x86: Disable Intel Processor Trace when VMXON in L1 guest

[Luwei Kang <luwei.kang@intel.com>]

Disable Intel Processor Trace VMX operation(IA32_VMX_MISC[bit 14] is 0)
in L1 guest. As mentioned in SDM, on these type of processors, execution
of the VMXON instruction will  clears IA32_RTIT_CTL.TraceEn and any
attempt to write IA32_RTIT_CTL causes a general-protection xception (#GP).

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 xen/arch/x86/hvm/vmx/vvmx.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index e97db33..30c7876 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -26,6 +26,7 @@
 #include <asm/hvm/vmx/vmx.h>
 #include <asm/hvm/vmx/vvmx.h>
 #include <asm/hvm/nestedhvm.h>
+#include <asm/ipt.h>
 
 static DEFINE_PER_CPU(u64 *, vvmcs_buf);
 
@@ -1519,6 +1520,14 @@ int nvmx_handle_vmxon(struct cpu_user_regs *regs)
     v->arch.hvm_vmx.launched = 0;
     vmsucceed(regs);
 
+    if ( v->arch.hvm_vmx.ipt_desc )
+    {
+        v->arch.hvm_vmx.ipt_desc->ipt_guest.ctl = 0;
+        vmx_vmcs_enter(current);
+        __vmwrite(GUEST_IA32_RTIT_CTL, 0);
+        vmx_vmcs_exit(current);
+    }
+
     return X86EMUL_OKAY;
 }
 
@@ -2143,8 +2152,8 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         data = hvm_cr4_guest_valid_bits(d, false);
         break;
     case MSR_IA32_VMX_MISC:
-        /* Do not support CR3-target feature now */
-        data = host_data & ~VMX_MISC_CR3_TARGET;
+        /* Do not support CR3-target and PT VMX feature now */
+        data = host_data & ~(VMX_MISC_CR3_TARGET | VMX_MISC_PT_ENABLE);
         break;
     case MSR_IA32_VMX_EPT_VPID_CAP:
         data = nept_get_ept_vpid_cap();
-- 
1.8.3.1


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