From: Luwei Kang <luwei.kang@intel.com>
To: xen-devel@lists.xen.org
Cc: kevin.tian@intel.com, sstabellini@kernel.org,
wei.liu2@citrix.com, jun.nakajima@intel.com,
George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com,
ian.jackson@eu.citrix.com, tim@xen.org, julien.grall@arm.com,
jbeulich@suse.com, Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v2 10/10] x86: Handle new asynchronous exit qualification
Date: Wed, 30 May 2018 21:28:04 +0800 [thread overview]
Message-ID: <1527686884-5917-11-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1527686884-5917-1-git-send-email-luwei.kang@intel.com>
Using EPT to translate PT output addresses introduces the possibility of
taking events on PT output reads and writes. Event possibilities include
EPT violations, EPT misconfigurations, PML log-full VM exits, and APIC
access VM exits.
EPT violations:
a. Intel PT buffer is a MMIO address in guest. Actually, it can be a
MMIO address (SDM 35.2.6.1), but in order do not affect other
passthrough/emulate device in guest. Ferbid use MMIO addr at present.
b. Intel PT buffer is a RAM non-writable address. Don't need emulate
and inject a #GP to guest.
c. EPT table entry write protect for Live Migration. Do nothing and
handled as usual.
EPT misconfiguration:
Nothing to do.
PML log-full VM exits:
Intel PT trace output a new page, this behavior will be recorded to
PML page may cause PML log-FULL VM-exit. Nothing to do.
APIC access VM exits:
PT output region shouldn't have overlap with 4KB APIC MMIO region as
defined by the IA32_APIC_BASE (SDM 35.2.6.4) but no error for this
case in hardware. Crash guest in hypervisor.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
xen/arch/x86/hvm/hvm.c | 8 ++++++--
xen/arch/x86/hvm/vmx/vmx.c | 5 +++++
xen/include/asm-x86/hvm/vmx/vmx.h | 8 +++++---
xen/include/xen/mm.h | 1 +
4 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index c23983c..7782160 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1712,7 +1712,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla,
struct vcpu *curr = current;
struct domain *currd = curr->domain;
struct p2m_domain *p2m, *hostp2m;
- int rc, fall_through = 0, paged = 0;
+ int rc = 0, fall_through = 0, paged = 0;
int sharing_enomem = 0;
vm_event_request_t *req_ptr = NULL;
bool_t ap2m_active, sync = 0;
@@ -1873,7 +1873,11 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla,
(npfec.write_access &&
(p2m_is_discard_write(p2mt) || (p2mt == p2m_ioreq_server))) )
{
- if ( !handle_mmio_with_translation(gla, gpa >> PAGE_SHIFT, npfec) )
+ /* Don't emulate and make guest crash when write to mmio address */
+ if ( npfec.async && (p2mt == p2m_mmio_dm) )
+ goto out_put_gfn;
+
+ if ( npfec.async || !handle_mmio_with_translation(gla, gpa >> PAGE_SHIFT, npfec) )
hvm_inject_hw_exception(TRAP_gp_fault, 0);
rc = 1;
goto out_put_gfn;
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index fa1ca0c..d0d00f8 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -3253,6 +3253,7 @@ static void ept_handle_violation(ept_qual_t q, paddr_t gpa)
.write_access = q.write,
.insn_fetch = q.fetch,
.present = q.eff_read || q.eff_write || q.eff_exec,
+ .async = q.async,
};
if ( tb_init_done )
@@ -4027,6 +4028,10 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs)
break;
case EXIT_REASON_APIC_ACCESS:
+ __vmread(EXIT_QUALIFICATION, &exit_qualification);
+ if ( exit_qualification & 0x10000 )
+ goto exit_and_crash;
+
if ( !vmx_handle_eoi_write() && !handle_mmio() )
hvm_inject_hw_exception(TRAP_gp_fault, 0);
break;
diff --git a/xen/include/asm-x86/hvm/vmx/vmx.h b/xen/include/asm-x86/hvm/vmx/vmx.h
index 89619e4..e7c5360 100644
--- a/xen/include/asm-x86/hvm/vmx/vmx.h
+++ b/xen/include/asm-x86/hvm/vmx/vmx.h
@@ -620,11 +620,13 @@ void vmx_pi_hooks_deassign(struct domain *d);
typedef union ept_qual {
unsigned long raw;
struct {
- bool read:1, write:1, fetch:1,
+ unsigned long read:1, write:1, fetch:1,
eff_read:1, eff_write:1, eff_exec:1, /* eff_user_exec */:1,
gla_valid:1,
- gla_fault:1; /* Valid iff gla_valid. */
- unsigned long /* pad */:55;
+ gla_fault:1, /* Valid iff gla_valid. */
+ :7,
+ async:1; /* Asynchronous to Instruction Execution (e.g. ipt) */
+ unsigned long /* pad */:47;
};
} __transparent__ ept_qual_t;
diff --git a/xen/include/xen/mm.h b/xen/include/xen/mm.h
index e928551..1546d4f 100644
--- a/xen/include/xen/mm.h
+++ b/xen/include/xen/mm.h
@@ -228,6 +228,7 @@ struct npfec {
unsigned int present:1;
unsigned int gla_valid:1;
unsigned int kind:2; /* npfec_kind_t */
+ unsigned int async:1;
};
/* memflags: */
--
1.8.3.1
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next prev parent reply other threads:[~2018-05-30 13:28 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-30 13:27 [PATCH v2 00/10] Intel Processor Trace virtulization enabling Luwei Kang
2018-05-30 13:27 ` [PATCH v2 01/10] x86: add an flag to enable Intel Processor Trace in guest Luwei Kang
2018-06-28 14:11 ` Jan Beulich
2018-07-03 10:18 ` Kang, Luwei
2018-07-03 11:58 ` Jan Beulich
2018-05-30 13:27 ` [PATCH v2 02/10] x86: Configure VMCS for Intel Processor Trace virtualization Luwei Kang
2018-05-30 13:27 ` [PATCH v2 03/10] x86: Add Intel Processor Trace support for cpuid Luwei Kang
2018-06-28 14:27 ` Jan Beulich
2018-07-12 7:21 ` Kang, Luwei
2018-07-12 7:48 ` Jan Beulich
2018-06-29 15:17 ` Jan Beulich
2018-07-03 10:19 ` Kang, Luwei
2018-07-03 10:25 ` Andrew Cooper
2018-05-30 13:27 ` [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions Luwei Kang
2018-06-28 14:44 ` Jan Beulich
2018-07-03 10:18 ` Kang, Luwei
2018-07-03 12:00 ` Jan Beulich
2018-05-30 13:27 ` [PATCH v2 05/10] x86: Implement Intel Processor Trace context switch Luwei Kang
2018-06-29 14:12 ` Jan Beulich
2018-07-03 10:18 ` Kang, Luwei
2018-07-03 12:04 ` Jan Beulich
2018-07-04 8:48 ` Kang, Luwei
2018-07-04 9:05 ` Jan Beulich
2018-07-04 9:41 ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 06/10] x86: Introduce a new function to get capability of Intel PT Luwei Kang
2018-06-29 14:35 ` Jan Beulich
2018-07-03 10:18 ` Kang, Luwei
2018-07-03 12:09 ` Jan Beulich
2018-07-04 8:48 ` Kang, Luwei
2018-07-04 9:09 ` Jan Beulich
2018-07-04 9:42 ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 07/10] x86: Add Intel Processor Trace MSRs read/write emulation Luwei Kang
2018-06-29 14:46 ` Jan Beulich
2018-07-03 10:18 ` Kang, Luwei
2018-07-03 12:10 ` Jan Beulich
2018-05-30 13:28 ` [PATCH v2 08/10] x86: Introduce a function to check the value of RTIT_CTL Luwei Kang
2018-06-29 14:56 ` Jan Beulich
2018-07-03 10:19 ` Kang, Luwei
2018-07-03 12:15 ` Jan Beulich
2018-05-30 13:28 ` [PATCH v2 09/10] x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-06-29 15:14 ` Jan Beulich
2018-07-03 10:19 ` Kang, Luwei
2018-05-30 13:28 ` Luwei Kang [this message]
2018-06-29 15:22 ` [PATCH v2 10/10] x86: Handle new asynchronous exit qualification Jan Beulich
2018-06-29 15:29 ` Andrew Cooper
2018-05-30 15:14 ` [PATCH v2 00/10] Intel Processor Trace virtulization enabling Julien Grall
2018-05-30 23:29 ` Kang, Luwei
2018-05-31 9:10 ` Julien Grall
2018-05-31 9:21 ` Kang, Luwei
2018-06-01 7:49 ` Jan Beulich
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