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From: Luwei Kang <luwei.kang@intel.com>
To: xen-devel@lists.xen.org
Cc: kevin.tian@intel.com, sstabellini@kernel.org,
	wei.liu2@citrix.com, jun.nakajima@intel.com,
	George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com,
	ian.jackson@eu.citrix.com, tim@xen.org, julien.grall@arm.com,
	jbeulich@suse.com, Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v2 02/10] x86: Configure VMCS for Intel Processor Trace virtualization
Date: Wed, 30 May 2018 21:27:56 +0800	[thread overview]
Message-ID: <1527686884-5917-3-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1527686884-5917-1-git-send-email-luwei.kang@intel.com>

This patch configure VMCS to make Intel Processor Trace
output address can be treat as guest physical address and
translated by EPT when ipt option is in guest mode.

Intel Processor Trace will be disabled in guest and the VMCS
configuration will be clear when part of the required
features is available in hardware or this feature is
disabled by user.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 xen/arch/x86/hvm/vmx/vmcs.c        | 37 ++++++++++++++++++++++++++++++++-----
 xen/include/asm-x86/hvm/vmx/vmcs.h |  7 +++++++
 2 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 70c2fb7..1a2ee60 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -40,6 +40,7 @@
 #include <asm/shadow.h>
 #include <asm/tboot.h>
 #include <asm/apic.h>
+#include <asm/ipt.h>
 
 static bool_t __read_mostly opt_vpid_enabled = 1;
 boolean_param("vpid", opt_vpid_enabled);
@@ -242,6 +243,9 @@ static int vmx_init_vmcs_config(void)
         rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap);
         if ( _vmx_misc_cap & VMX_MISC_VMWRITE_ALL )
             opt |= SECONDARY_EXEC_ENABLE_VMCS_SHADOWING;
+        if ( _vmx_misc_cap & VMX_MISC_PT_ENABLE )
+            opt |= SECONDARY_EXEC_PT_USE_GPA |
+                   SECONDARY_EXEC_CONCEAL_PT_PIP;
         if ( opt_vpid_enabled )
             opt |= SECONDARY_EXEC_ENABLE_VPID;
         if ( opt_unrestricted_guest_enabled )
@@ -343,7 +347,8 @@ static int vmx_init_vmcs_config(void)
 
     min = VM_EXIT_ACK_INTR_ON_EXIT;
     opt = VM_EXIT_SAVE_GUEST_PAT | VM_EXIT_LOAD_HOST_PAT |
-          VM_EXIT_CLEAR_BNDCFGS;
+          VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_CONCEAL_PT_PIP |
+          VM_EXIT_CLEAR_IA32_RTIT_CTL;
     min |= VM_EXIT_IA32E_MODE;
     _vmx_vmexit_control = adjust_vmx_controls(
         "VMExit Control", min, opt, MSR_IA32_VMX_EXIT_CTLS, &mismatch);
@@ -383,13 +388,29 @@ static int vmx_init_vmcs_config(void)
         _vmx_secondary_exec_control &= ~SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS;
 
     min = 0;
-    opt = VM_ENTRY_LOAD_GUEST_PAT | VM_ENTRY_LOAD_BNDCFGS;
+    opt = VM_ENTRY_LOAD_GUEST_PAT | VM_ENTRY_LOAD_BNDCFGS |
+          VM_ENTRY_CONCEAL_PT_PIP | VM_ENTRY_LOAD_IA32_RTIT_CTL;
     _vmx_vmentry_control = adjust_vmx_controls(
         "VMEntry Control", min, opt, MSR_IA32_VMX_ENTRY_CTLS, &mismatch);
 
     if ( mismatch )
         return -EINVAL;
 
+    if ( !(_vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) ||
+         !(_vmx_secondary_exec_control & SECONDARY_EXEC_PT_USE_GPA) ||
+         !(_vmx_vmexit_control & VM_EXIT_CLEAR_IA32_RTIT_CTL) ||
+         !(_vmx_vmentry_control & VM_ENTRY_LOAD_IA32_RTIT_CTL) ||
+         (ipt_mode == IPT_MODE_OFF) )
+    {
+        _vmx_secondary_exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA |
+                                         SECONDARY_EXEC_CONCEAL_PT_PIP);
+        _vmx_vmexit_control &= ~(VM_EXIT_CONCEAL_PT_PIP |
+                                 VM_EXIT_CLEAR_IA32_RTIT_CTL);
+        _vmx_vmentry_control &= ~(VM_ENTRY_CONCEAL_PT_PIP |
+                                  VM_ENTRY_LOAD_IA32_RTIT_CTL);
+        ipt_mode = IPT_MODE_OFF;
+    }
+
     if ( !vmx_pin_based_exec_control )
     {
         /* First time through. */
@@ -1029,10 +1050,16 @@ static int construct_vmcs(struct vcpu *v)
         v->arch.hvm_vmx.secondary_exec_control &= 
             ~(SECONDARY_EXEC_ENABLE_EPT | 
               SECONDARY_EXEC_UNRESTRICTED_GUEST |
-              SECONDARY_EXEC_ENABLE_INVPCID);
+              SECONDARY_EXEC_ENABLE_INVPCID |
+              SECONDARY_EXEC_PT_USE_GPA |
+              SECONDARY_EXEC_CONCEAL_PT_PIP);
         vmexit_ctl &= ~(VM_EXIT_SAVE_GUEST_PAT |
-                        VM_EXIT_LOAD_HOST_PAT);
-        vmentry_ctl &= ~VM_ENTRY_LOAD_GUEST_PAT;
+                        VM_EXIT_LOAD_HOST_PAT |
+                        VM_EXIT_CONCEAL_PT_PIP |
+                        VM_EXIT_CLEAR_IA32_RTIT_CTL);
+        vmentry_ctl &= ~(VM_ENTRY_LOAD_GUEST_PAT |
+                         VM_ENTRY_CONCEAL_PT_PIP |
+                         VM_ENTRY_LOAD_IA32_RTIT_CTL);
     }
 
     /* Disable Virtualize x2APIC mode by default. */
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h b/xen/include/asm-x86/hvm/vmx/vmcs.h
index 06c3179..2990992 100644
--- a/xen/include/asm-x86/hvm/vmx/vmcs.h
+++ b/xen/include/asm-x86/hvm/vmx/vmcs.h
@@ -223,6 +223,8 @@ extern u32 vmx_pin_based_exec_control;
 #define VM_EXIT_LOAD_HOST_EFER          0x00200000
 #define VM_EXIT_SAVE_PREEMPT_TIMER      0x00400000
 #define VM_EXIT_CLEAR_BNDCFGS           0x00800000
+#define VM_EXIT_CONCEAL_PT_PIP          0x01000000
+#define VM_EXIT_CLEAR_IA32_RTIT_CTL     0x02000000
 extern u32 vmx_vmexit_control;
 
 #define VM_ENTRY_IA32E_MODE             0x00000200
@@ -232,6 +234,8 @@ extern u32 vmx_vmexit_control;
 #define VM_ENTRY_LOAD_GUEST_PAT         0x00004000
 #define VM_ENTRY_LOAD_GUEST_EFER        0x00008000
 #define VM_ENTRY_LOAD_BNDCFGS           0x00010000
+#define VM_ENTRY_CONCEAL_PT_PIP         0x00020000
+#define VM_ENTRY_LOAD_IA32_RTIT_CTL     0x00040000
 extern u32 vmx_vmentry_control;
 
 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
@@ -250,7 +254,9 @@ extern u32 vmx_vmentry_control;
 #define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING    0x00004000
 #define SECONDARY_EXEC_ENABLE_PML               0x00020000
 #define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS   0x00040000
+#define SECONDARY_EXEC_CONCEAL_PT_PIP           0x00080000
 #define SECONDARY_EXEC_XSAVES                   0x00100000
+#define SECONDARY_EXEC_PT_USE_GPA               0x01000000
 #define SECONDARY_EXEC_TSC_SCALING              0x02000000
 extern u32 vmx_secondary_exec_control;
 
@@ -271,6 +277,7 @@ extern u32 vmx_secondary_exec_control;
 #define VMX_VPID_INVVPID_SINGLE_CONTEXT_RETAINING_GLOBAL 0x80000000000ULL
 extern u64 vmx_ept_vpid_cap;
 
+#define VMX_MISC_PT_ENABLE                      0x00004000
 #define VMX_MISC_CR3_TARGET                     0x01ff0000
 #define VMX_MISC_VMWRITE_ALL                    0x20000000
 
-- 
1.8.3.1


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  parent reply	other threads:[~2018-05-30 13:27 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-30 13:27 [PATCH v2 00/10] Intel Processor Trace virtulization enabling Luwei Kang
2018-05-30 13:27 ` [PATCH v2 01/10] x86: add an flag to enable Intel Processor Trace in guest Luwei Kang
2018-06-28 14:11   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 11:58       ` Jan Beulich
2018-05-30 13:27 ` Luwei Kang [this message]
2018-05-30 13:27 ` [PATCH v2 03/10] x86: Add Intel Processor Trace support for cpuid Luwei Kang
2018-06-28 14:27   ` Jan Beulich
2018-07-12  7:21     ` Kang, Luwei
2018-07-12  7:48       ` Jan Beulich
2018-06-29 15:17   ` Jan Beulich
2018-07-03 10:19     ` Kang, Luwei
2018-07-03 10:25       ` Andrew Cooper
2018-05-30 13:27 ` [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions Luwei Kang
2018-06-28 14:44   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:00       ` Jan Beulich
2018-05-30 13:27 ` [PATCH v2 05/10] x86: Implement Intel Processor Trace context switch Luwei Kang
2018-06-29 14:12   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:04       ` Jan Beulich
2018-07-04  8:48         ` Kang, Luwei
2018-07-04  9:05           ` Jan Beulich
2018-07-04  9:41             ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 06/10] x86: Introduce a new function to get capability of Intel PT Luwei Kang
2018-06-29 14:35   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:09       ` Jan Beulich
2018-07-04  8:48         ` Kang, Luwei
2018-07-04  9:09           ` Jan Beulich
2018-07-04  9:42             ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 07/10] x86: Add Intel Processor Trace MSRs read/write emulation Luwei Kang
2018-06-29 14:46   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:10       ` Jan Beulich
2018-05-30 13:28 ` [PATCH v2 08/10] x86: Introduce a function to check the value of RTIT_CTL Luwei Kang
2018-06-29 14:56   ` Jan Beulich
2018-07-03 10:19     ` Kang, Luwei
2018-07-03 12:15       ` Jan Beulich
2018-05-30 13:28 ` [PATCH v2 09/10] x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-06-29 15:14   ` Jan Beulich
2018-07-03 10:19     ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 10/10] x86: Handle new asynchronous exit qualification Luwei Kang
2018-06-29 15:22   ` Jan Beulich
2018-06-29 15:29     ` Andrew Cooper
2018-05-30 15:14 ` [PATCH v2 00/10] Intel Processor Trace virtulization enabling Julien Grall
2018-05-30 23:29   ` Kang, Luwei
2018-05-31  9:10     ` Julien Grall
2018-05-31  9:21       ` Kang, Luwei
2018-06-01  7:49       ` Jan Beulich

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