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From: Luwei Kang <luwei.kang@intel.com>
To: xen-devel@lists.xen.org
Cc: kevin.tian@intel.com, sstabellini@kernel.org,
	wei.liu2@citrix.com, jun.nakajima@intel.com,
	George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com,
	ian.jackson@eu.citrix.com, tim@xen.org, julien.grall@arm.com,
	jbeulich@suse.com, Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions
Date: Wed, 30 May 2018 21:27:58 +0800	[thread overview]
Message-ID: <1527686884-5917-5-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1527686884-5917-1-git-send-email-luwei.kang@intel.com>

Add Intel Processor Trace MSRs and bit definitions.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 xen/include/asm-x86/msr-index.h | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 8fbccc8..7c02653 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -548,4 +548,41 @@
 #define MSR_PKGC9_IRTL			0x00000634
 #define MSR_PKGC10_IRTL			0x00000635
 
+/* Intel PT MSRs */
+#define MSR_IA32_RTIT_CTL		0x00000570
+#define RTIT_CTL_TRACEEN		(1ULL << 0)
+#define RTIT_CTL_CYCEN			(1ULL << 1)
+#define RTIT_CTL_OS			(1ULL << 2)
+#define RTIT_CTL_USR			(1ULL << 3)
+#define RTIT_CTL_PWR_EVT_EN		(1ULL << 4)
+#define RTIT_CTL_FUP_ON_PTW		(1ULL << 5)
+#define RTIT_CTL_FABRIC_EN		(1ULL << 6)
+#define RTIT_CTL_CR3_FILTER		(1ULL << 7)
+#define RTIT_CTL_TOPA			(1ULL << 8)
+#define RTIT_CTL_MTC_EN			(1ULL << 9)
+#define RTIT_CTL_TSC_EN			(1ULL << 10)
+#define RTIT_CTL_DIS_RETC		(1ULL << 11)
+#define RTIT_CTL_PTW_EN			(1ULL << 12)
+#define RTIT_CTL_BRANCH_EN		(1ULL << 13)
+#define RTIT_CTL_MTC_FREQ_OFFSET	14
+#define RTIT_CTL_MTC_FREQ		(0x0fULL << RTIT_CTL_MTC_FREQ_OFFSET)
+#define RTIT_CTL_CYC_THRESH_OFFSET	19
+#define RTIT_CTL_CYC_THRESH		(0x0fULL << RTIT_CTL_CYC_THRESH_OFFSET)
+#define RTIT_CTL_PSB_FREQ_OFFSET	24
+#define RTIT_CTL_PSB_FREQ		(0x0fULL << RTIT_CTL_PSB_FREQ_OFFSET)
+#define RTIT_CTL_ADDR_OFFSET(n)		(32 + 4 * (n))
+#define RTIT_CTL_ADDR(n)		(0x0fULL << RTIT_CTL_ADDR_OFFSET(n))
+#define MSR_IA32_RTIT_STATUS		0x00000571
+#define RTIT_STATUS_FILTER_EN		(1ULL << 0)
+#define RTIT_STATUS_CONTEXT_EN		(1ULL << 1)
+#define RTIT_STATUS_TRIGGER_EN		(1ULL << 2)
+#define RTIT_STATUS_ERROR		(1ULL << 4)
+#define RTIT_STATUS_STOPPED		(1ULL << 5)
+#define RTIT_STATUS_BYTECNT		(0x1ffffULL << 32)
+#define MSR_IA32_RTIT_CR3_MATCH		0x00000572
+#define MSR_IA32_RTIT_OUTPUT_BASE	0x00000560
+#define MSR_IA32_RTIT_OUTPUT_MASK	0x00000561
+#define MSR_IA32_RTIT_ADDR_A(n)		(0x00000580 + (n) * 2)
+#define MSR_IA32_RTIT_ADDR_B(n)		(0x00000581 + (n) * 2)
+
 #endif /* __ASM_MSR_INDEX_H */
-- 
1.8.3.1


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  parent reply	other threads:[~2018-05-30 13:27 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-30 13:27 [PATCH v2 00/10] Intel Processor Trace virtulization enabling Luwei Kang
2018-05-30 13:27 ` [PATCH v2 01/10] x86: add an flag to enable Intel Processor Trace in guest Luwei Kang
2018-06-28 14:11   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 11:58       ` Jan Beulich
2018-05-30 13:27 ` [PATCH v2 02/10] x86: Configure VMCS for Intel Processor Trace virtualization Luwei Kang
2018-05-30 13:27 ` [PATCH v2 03/10] x86: Add Intel Processor Trace support for cpuid Luwei Kang
2018-06-28 14:27   ` Jan Beulich
2018-07-12  7:21     ` Kang, Luwei
2018-07-12  7:48       ` Jan Beulich
2018-06-29 15:17   ` Jan Beulich
2018-07-03 10:19     ` Kang, Luwei
2018-07-03 10:25       ` Andrew Cooper
2018-05-30 13:27 ` Luwei Kang [this message]
2018-06-28 14:44   ` [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:00       ` Jan Beulich
2018-05-30 13:27 ` [PATCH v2 05/10] x86: Implement Intel Processor Trace context switch Luwei Kang
2018-06-29 14:12   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:04       ` Jan Beulich
2018-07-04  8:48         ` Kang, Luwei
2018-07-04  9:05           ` Jan Beulich
2018-07-04  9:41             ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 06/10] x86: Introduce a new function to get capability of Intel PT Luwei Kang
2018-06-29 14:35   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:09       ` Jan Beulich
2018-07-04  8:48         ` Kang, Luwei
2018-07-04  9:09           ` Jan Beulich
2018-07-04  9:42             ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 07/10] x86: Add Intel Processor Trace MSRs read/write emulation Luwei Kang
2018-06-29 14:46   ` Jan Beulich
2018-07-03 10:18     ` Kang, Luwei
2018-07-03 12:10       ` Jan Beulich
2018-05-30 13:28 ` [PATCH v2 08/10] x86: Introduce a function to check the value of RTIT_CTL Luwei Kang
2018-06-29 14:56   ` Jan Beulich
2018-07-03 10:19     ` Kang, Luwei
2018-07-03 12:15       ` Jan Beulich
2018-05-30 13:28 ` [PATCH v2 09/10] x86: Disable Intel Processor Trace when VMXON in L1 guest Luwei Kang
2018-06-29 15:14   ` Jan Beulich
2018-07-03 10:19     ` Kang, Luwei
2018-05-30 13:28 ` [PATCH v2 10/10] x86: Handle new asynchronous exit qualification Luwei Kang
2018-06-29 15:22   ` Jan Beulich
2018-06-29 15:29     ` Andrew Cooper
2018-05-30 15:14 ` [PATCH v2 00/10] Intel Processor Trace virtulization enabling Julien Grall
2018-05-30 23:29   ` Kang, Luwei
2018-05-31  9:10     ` Julien Grall
2018-05-31  9:21       ` Kang, Luwei
2018-06-01  7:49       ` Jan Beulich

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