From mboxrd@z Thu Jan 1 00:00:00 1970 From: Luwei Kang Subject: [PATCH v2 04/10] x86: Add Intel Processor Trace MSRs and bit definitions Date: Wed, 30 May 2018 21:27:58 +0800 Message-ID: <1527686884-5917-5-git-send-email-luwei.kang@intel.com> References: <1527686884-5917-1-git-send-email-luwei.kang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1527686884-5917-1-git-send-email-luwei.kang@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To: xen-devel@lists.xen.org Cc: kevin.tian@intel.com, sstabellini@kernel.org, wei.liu2@citrix.com, jun.nakajima@intel.com, George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, tim@xen.org, julien.grall@arm.com, jbeulich@suse.com, Luwei Kang List-Id: xen-devel@lists.xenproject.org QWRkIEludGVsIFByb2Nlc3NvciBUcmFjZSBNU1JzIGFuZCBiaXQgZGVmaW5pdGlvbnMuCgpTaWdu ZWQtb2ZmLWJ5OiBMdXdlaSBLYW5nIDxsdXdlaS5rYW5nQGludGVsLmNvbT4KLS0tCiB4ZW4vaW5j bHVkZS9hc20teDg2L21zci1pbmRleC5oIHwgMzcgKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDM3IGluc2VydGlvbnMoKykKCmRpZmYgLS1naXQg YS94ZW4vaW5jbHVkZS9hc20teDg2L21zci1pbmRleC5oIGIveGVuL2luY2x1ZGUvYXNtLXg4Ni9t c3ItaW5kZXguaAppbmRleCA4ZmJjY2M4Li43YzAyNjUzIDEwMDY0NAotLS0gYS94ZW4vaW5jbHVk ZS9hc20teDg2L21zci1pbmRleC5oCisrKyBiL3hlbi9pbmNsdWRlL2FzbS14ODYvbXNyLWluZGV4 LmgKQEAgLTU0OCw0ICs1NDgsNDEgQEAKICNkZWZpbmUgTVNSX1BLR0M5X0lSVEwJCQkweDAwMDAw NjM0CiAjZGVmaW5lIE1TUl9QS0dDMTBfSVJUTAkJCTB4MDAwMDA2MzUKIAorLyogSW50ZWwgUFQg TVNScyAqLworI2RlZmluZSBNU1JfSUEzMl9SVElUX0NUTAkJMHgwMDAwMDU3MAorI2RlZmluZSBS VElUX0NUTF9UUkFDRUVOCQkoMVVMTCA8PCAwKQorI2RlZmluZSBSVElUX0NUTF9DWUNFTgkJCSgx VUxMIDw8IDEpCisjZGVmaW5lIFJUSVRfQ1RMX09TCQkJKDFVTEwgPDwgMikKKyNkZWZpbmUgUlRJ VF9DVExfVVNSCQkJKDFVTEwgPDwgMykKKyNkZWZpbmUgUlRJVF9DVExfUFdSX0VWVF9FTgkJKDFV TEwgPDwgNCkKKyNkZWZpbmUgUlRJVF9DVExfRlVQX09OX1BUVwkJKDFVTEwgPDwgNSkKKyNkZWZp bmUgUlRJVF9DVExfRkFCUklDX0VOCQkoMVVMTCA8PCA2KQorI2RlZmluZSBSVElUX0NUTF9DUjNf RklMVEVSCQkoMVVMTCA8PCA3KQorI2RlZmluZSBSVElUX0NUTF9UT1BBCQkJKDFVTEwgPDwgOCkK KyNkZWZpbmUgUlRJVF9DVExfTVRDX0VOCQkJKDFVTEwgPDwgOSkKKyNkZWZpbmUgUlRJVF9DVExf VFNDX0VOCQkJKDFVTEwgPDwgMTApCisjZGVmaW5lIFJUSVRfQ1RMX0RJU19SRVRDCQkoMVVMTCA8 PCAxMSkKKyNkZWZpbmUgUlRJVF9DVExfUFRXX0VOCQkJKDFVTEwgPDwgMTIpCisjZGVmaW5lIFJU SVRfQ1RMX0JSQU5DSF9FTgkJKDFVTEwgPDwgMTMpCisjZGVmaW5lIFJUSVRfQ1RMX01UQ19GUkVR X09GRlNFVAkxNAorI2RlZmluZSBSVElUX0NUTF9NVENfRlJFUQkJKDB4MGZVTEwgPDwgUlRJVF9D VExfTVRDX0ZSRVFfT0ZGU0VUKQorI2RlZmluZSBSVElUX0NUTF9DWUNfVEhSRVNIX09GRlNFVAkx OQorI2RlZmluZSBSVElUX0NUTF9DWUNfVEhSRVNICQkoMHgwZlVMTCA8PCBSVElUX0NUTF9DWUNf VEhSRVNIX09GRlNFVCkKKyNkZWZpbmUgUlRJVF9DVExfUFNCX0ZSRVFfT0ZGU0VUCTI0CisjZGVm aW5lIFJUSVRfQ1RMX1BTQl9GUkVRCQkoMHgwZlVMTCA8PCBSVElUX0NUTF9QU0JfRlJFUV9PRkZT RVQpCisjZGVmaW5lIFJUSVRfQ1RMX0FERFJfT0ZGU0VUKG4pCQkoMzIgKyA0ICogKG4pKQorI2Rl ZmluZSBSVElUX0NUTF9BRERSKG4pCQkoMHgwZlVMTCA8PCBSVElUX0NUTF9BRERSX09GRlNFVChu KSkKKyNkZWZpbmUgTVNSX0lBMzJfUlRJVF9TVEFUVVMJCTB4MDAwMDA1NzEKKyNkZWZpbmUgUlRJ VF9TVEFUVVNfRklMVEVSX0VOCQkoMVVMTCA8PCAwKQorI2RlZmluZSBSVElUX1NUQVRVU19DT05U RVhUX0VOCQkoMVVMTCA8PCAxKQorI2RlZmluZSBSVElUX1NUQVRVU19UUklHR0VSX0VOCQkoMVVM TCA8PCAyKQorI2RlZmluZSBSVElUX1NUQVRVU19FUlJPUgkJKDFVTEwgPDwgNCkKKyNkZWZpbmUg UlRJVF9TVEFUVVNfU1RPUFBFRAkJKDFVTEwgPDwgNSkKKyNkZWZpbmUgUlRJVF9TVEFUVVNfQllU RUNOVAkJKDB4MWZmZmZVTEwgPDwgMzIpCisjZGVmaW5lIE1TUl9JQTMyX1JUSVRfQ1IzX01BVENI CQkweDAwMDAwNTcyCisjZGVmaW5lIE1TUl9JQTMyX1JUSVRfT1VUUFVUX0JBU0UJMHgwMDAwMDU2 MAorI2RlZmluZSBNU1JfSUEzMl9SVElUX09VVFBVVF9NQVNLCTB4MDAwMDA1NjEKKyNkZWZpbmUg TVNSX0lBMzJfUlRJVF9BRERSX0EobikJCSgweDAwMDAwNTgwICsgKG4pICogMikKKyNkZWZpbmUg TVNSX0lBMzJfUlRJVF9BRERSX0IobikJCSgweDAwMDAwNTgxICsgKG4pICogMikKKwogI2VuZGlm IC8qIF9fQVNNX01TUl9JTkRFWF9IICovCi0tIAoxLjguMy4xCgoKX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVsIG1haWxpbmcgbGlzdApYZW4t ZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0cHM6Ly9saXN0cy54ZW5wcm9qZWN0Lm9yZy9t YWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA==