From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Xen-devel <xen-devel@lists.xen.org>
Cc: "Andrew Cooper" <andrew.cooper3@citrix.com>,
"Wei Liu" <wei.liu2@citrix.com>,
"Jan Beulich" <JBeulich@suse.com>,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: [PATCH 11/11] x86/dbg: Cleanup of legacy dr6 constants
Date: Mon, 4 Jun 2018 14:59:15 +0100 [thread overview]
Message-ID: <1528120755-17455-12-git-send-email-andrew.cooper3@citrix.com> (raw)
In-Reply-To: <1528120755-17455-1-git-send-email-andrew.cooper3@citrix.com>
Replace the few remaining uses with X86_DR6_* constants.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Wei Liu <wei.liu2@citrix.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
---
xen/arch/x86/pv/emul-priv-op.c | 2 +-
xen/arch/x86/traps.c | 2 +-
xen/include/asm-x86/debugreg.h | 17 -----------------
3 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 45788b2..bec6ee9 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch/x86/pv/emul-priv-op.c
@@ -1365,7 +1365,7 @@ int pv_emulate_privileged_op(struct cpu_user_regs *regs)
}
if ( ctxt.ctxt.retire.singlestep )
- ctxt.bpmatch |= DR_STEP;
+ ctxt.bpmatch |= X86_DR6_BS;
if ( ctxt.bpmatch &&
!(curr->arch.pv_vcpu.trap_bounce.flags & TBF_EXCEPTION) )
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 8ef22b4..362e209 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -1830,7 +1830,7 @@ void do_debug(struct cpu_user_regs *regs)
fatal_trap(regs, 0);
}
- if ( dr6 & (DR_TRAP3 | DR_TRAP2 | DR_TRAP1 | DR_TRAP0) )
+ if ( dr6 & X86_DR6_BP_MASK )
{
unsigned int bp, dr7 = read_debugreg(7) >> DR_CONTROL_SHIFT;
diff --git a/xen/include/asm-x86/debugreg.h b/xen/include/asm-x86/debugreg.h
index f6b361e..587ed9d 100644
--- a/xen/include/asm-x86/debugreg.h
+++ b/xen/include/asm-x86/debugreg.h
@@ -1,15 +1,6 @@
#ifndef _X86_DEBUGREG_H
#define _X86_DEBUGREG_H
-
-/* Indicate the register numbers for a number of the specific
- debug registers. Registers 0-3 contain the addresses we wish to trap on */
-
-#define DR_FIRSTADDR 0
-#define DR_LASTADDR 3
-#define DR_STATUS 6
-#define DR_CONTROL 7
-
/*
* DR6 status bits.
* N.B. For backwards compatibility, X86_DR6_RTM has inverted polarity.
@@ -29,14 +20,6 @@
#define X86_DR6_KNOWN_MASK \
(X86_DR6_BP_MASK | X86_DR6_BD | X86_DR6_BS | X86_DR6_BT | X86_DR6_RTM)
-#define DR_TRAP0 (0x1) /* db0 */
-#define DR_TRAP1 (0x2) /* db1 */
-#define DR_TRAP2 (0x4) /* db2 */
-#define DR_TRAP3 (0x8) /* db3 */
-#define DR_STEP (0x4000) /* single-step */
-#define DR_SWITCH (0x8000) /* task switch */
-#define DR_NOT_RTM (0x10000) /* clear: #BP inside RTM region */
-
#define X86_DR6_DEFAULT 0xffff0ff0ul /* Default %dr6 value. */
/* Now define a bunch of things for manipulating the control register.
--
2.1.4
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next prev parent reply other threads:[~2018-06-04 13:59 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-04 13:59 [PATCH 00/11] Fixes to debugging facilities Andrew Cooper
2018-06-04 13:59 ` [PATCH 01/11] x86/svm Fixes and cleanup to svm_inject_event() Andrew Cooper
2018-06-06 13:37 ` Jan Beulich
2018-07-16 13:33 ` Andrew Cooper
2018-07-17 2:01 ` Boris Ostrovsky
2018-06-04 13:59 ` [PATCH 02/11] x86/vmx: Don't clobber %dr6 while debugging state is lazy Andrew Cooper
2018-06-06 10:16 ` Roger Pau Monné
2018-06-06 13:50 ` Jan Beulich
2018-06-06 14:16 ` Andrew Cooper
2018-06-07 11:05 ` Jan Beulich
2018-06-08 15:58 ` Andrew Cooper
2018-06-08 16:10 ` Jan Beulich
2018-07-17 9:28 ` Andrew Cooper
2018-07-19 2:14 ` Tian, Kevin
2018-06-04 13:59 ` [PATCH 03/11] x86: Initialise debug registers correctly Andrew Cooper
2018-06-06 10:34 ` Roger Pau Monné
2018-06-08 15:23 ` Andrew Cooper
2018-06-06 13:56 ` Jan Beulich
2018-06-08 15:42 ` Andrew Cooper
2018-06-08 16:14 ` Jan Beulich
2018-06-04 13:59 ` [PATCH 04/11] x86: Fix calculation of %dr6/7 reserved bits Andrew Cooper
2018-06-06 14:16 ` Jan Beulich
2018-06-06 14:50 ` Andrew Cooper
2018-06-06 14:52 ` Andrew Cooper
2018-06-06 15:11 ` Jan Beulich
2018-06-06 15:49 ` Roger Pau Monné
2018-06-06 15:59 ` Andrew Cooper
2018-06-06 17:36 ` Roger Pau Monné
2018-06-04 13:59 ` [PATCH 05/11] x86/emul: Unfold %cr4.de handling in x86emul_read_dr() Andrew Cooper
2018-06-06 14:20 ` Jan Beulich
2018-06-08 16:03 ` Andrew Cooper
2018-06-08 16:16 ` Jan Beulich
2018-06-06 15:54 ` Roger Pau Monné
2018-06-04 13:59 ` [PATCH 06/11] x86: Reorganise and rename debug register fields in struct vcpu Andrew Cooper
2018-06-06 15:00 ` Jan Beulich
2018-06-06 15:21 ` Andrew Cooper
2018-06-07 10:59 ` Jan Beulich
2018-06-06 16:22 ` Roger Pau Monné
2018-06-04 13:59 ` [PATCH 07/11] x86/emul: Add pending_dbg field to x86_event Andrew Cooper
2018-06-06 16:46 ` Roger Pau Monné
2018-06-06 16:50 ` Andrew Cooper
2018-06-06 17:03 ` Roger Pau Monné
2018-06-08 12:34 ` Jan Beulich
2018-06-08 12:48 ` Andrew Cooper
2018-06-04 13:59 ` [PATCH 08/11] x86/hvm: RFC - PROBABLY BROKEN - Defer all debugging/monitor actions to {svm, vmx}_inject_event() Andrew Cooper
2018-06-04 14:53 ` Razvan Cojocaru
2018-06-04 15:07 ` Razvan Cojocaru
2018-06-06 17:02 ` Roger Pau Monné
2018-06-08 13:00 ` Jan Beulich
2018-06-08 13:13 ` Andrew Cooper
2018-06-04 13:59 ` [PATCH 09/11] x86: Fix merging of new status bits into %dr6 Andrew Cooper
2018-06-06 17:09 ` Roger Pau Monné
2018-06-08 13:09 ` Jan Beulich
2018-06-04 13:59 ` [PATCH 10/11] x86/vmx: Work around VMEntry failure when Single Stepping in an STI shadow Andrew Cooper
2018-09-03 10:39 ` Ping VT-x: " Andrew Cooper
2018-09-04 5:27 ` Tian, Kevin
2018-06-04 13:59 ` Andrew Cooper [this message]
2018-06-06 17:10 ` [PATCH 11/11] x86/dbg: Cleanup of legacy dr6 constants Roger Pau Monné
2018-06-08 13:12 ` Jan Beulich
2018-06-04 15:39 ` [PATCH 00/11] Fixes to debugging facilities Andrew Cooper
2018-06-04 17:09 ` Razvan Cojocaru
2018-06-04 17:18 ` Andrew Cooper
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