[PATCH 2/6] x86/msr: Cleanup of misc constants

[Andrew Cooper <andrew.cooper3@citrix.com>]

Begin the process of cleaning up msr-index.h.  Order the MSRs at the
head of the file by index, use spaces for indentation, _AC() for bit
positions, and add a comment describing the expected style.  Abbreviate
the ARCH_CAPS_* constants to reduce code volume.

Leave a trailing comment to logically split the file in two, between the
now-consistent head, and legacy tail which will be improved moving
forwards.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Wei Liu <wei.liu2@citrix.com>
CC: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/spec_ctrl.c        |  8 +++---
 xen/include/asm-x86/msr-index.h | 59 ++++++++++++++++++++++++++---------------
 2 files changed, 41 insertions(+), 26 deletions(-)

diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 08e6784..4db2ae0 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -215,8 +215,8 @@ static void __init print_details(enum ind_thunk thunk, uint64_t caps)
            (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP"     : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_SSBD))  ? " SSBD"      : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB))  ? " IBPB"      : "",
-           (caps & ARCH_CAPABILITIES_IBRS_ALL)      ? " IBRS_ALL"  : "",
-           (caps & ARCH_CAPABILITIES_RDCL_NO)       ? " RDCL_NO"   : "",
+           (caps & ARCH_CAPS_IBRS_ALL)              ? " IBRS_ALL"  : "",
+           (caps & ARCH_CAPS_RDCL_NO)               ? " RDCL_NO"   : "",
            (caps & ARCH_CAPS_RSBA)                  ? " RSBA"      : "",
            (caps & ARCH_CAPS_SSB_NO)                ? " SSB_NO"    : "");
 
@@ -429,11 +429,11 @@ static __init void xpti_init_default(bool force)
         return;
 
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
-        caps = ARCH_CAPABILITIES_RDCL_NO;
+        caps = ARCH_CAPS_RDCL_NO;
     else if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
         rdmsrl(MSR_ARCH_CAPABILITIES, caps);
 
-    if ( caps & ARCH_CAPABILITIES_RDCL_NO )
+    if ( caps & ARCH_CAPS_RDCL_NO )
         opt_xpti = 0;
     else
         opt_xpti = OPT_XPTI_DOM0 | OPT_XPTI_DOMU;
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 1b10f3e..2c9b75f 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -1,32 +1,34 @@
 #ifndef __ASM_MSR_INDEX_H
 #define __ASM_MSR_INDEX_H
 
-/* CPU model specific register (MSR) numbers */
-
-/* x86-64 specific MSRs */
-#define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
-#define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
-#define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
-#define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
-#define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
-#define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
-#define MSR_SHADOW_GS_BASE	0xc0000102 /* SwapGS GS shadow */
-#define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */
+/*
+ * CPU model specific register (MSR) numbers
+ *
+ * Definitions for an MSR should follow this style:
+ *
+ * #define MSR_$NAME                    0x$INDEX
+ * #define $NAME_$BIT1                  (_AC(1, ULL) << $POS1)
+ * #define $NAME_$BIT2                  (_AC(1, ULL) << $POS2)
+ *
+ * Blocks of related constants should be sorted by MSR index.  The constant
+ * names should be as concise as possible, and the bit names may have an
+ * abbreviated name.
+ */
 
 /* Speculation Controls. */
-#define MSR_SPEC_CTRL			0x00000048
-#define SPEC_CTRL_IBRS			(_AC(1, ULL) << 0)
-#define SPEC_CTRL_STIBP			(_AC(1, ULL) << 1)
-#define SPEC_CTRL_SSBD			(_AC(1, ULL) << 2)
+#define MSR_SPEC_CTRL                   0x00000048
+#define SPEC_CTRL_IBRS                  (_AC(1, ULL) <<  0)
+#define SPEC_CTRL_STIBP                 (_AC(1, ULL) <<  1)
+#define SPEC_CTRL_SSBD                  (_AC(1, ULL) <<  2)
 
-#define MSR_PRED_CMD			0x00000049
-#define PRED_CMD_IBPB			(_AC(1, ULL) << 0)
+#define MSR_PRED_CMD                    0x00000049
+#define PRED_CMD_IBPB                   (_AC(1, ULL) <<  0)
 
-#define MSR_ARCH_CAPABILITIES		0x0000010a
-#define ARCH_CAPABILITIES_RDCL_NO	(_AC(1, ULL) << 0)
-#define ARCH_CAPABILITIES_IBRS_ALL	(_AC(1, ULL) << 1)
-#define ARCH_CAPS_RSBA			(_AC(1, ULL) << 2)
-#define ARCH_CAPS_SSB_NO		(_AC(1, ULL) << 4)
+#define MSR_ARCH_CAPABILITIES           0x0000010a
+#define ARCH_CAPS_RDCL_NO               (_AC(1, ULL) <<  0)
+#define ARCH_CAPS_IBRS_ALL              (_AC(1, ULL) <<  1)
+#define ARCH_CAPS_RSBA                  (_AC(1, ULL) <<  2)
+#define ARCH_CAPS_SSB_NO                (_AC(1, ULL) <<  4)
 
 #define MSR_EFER                        0xc0000080 /* Extended Feature Enable Register */
 #define EFER_SCE                        (_AC(1, ULL) <<  0) /* SYSCALL Enable */
@@ -40,6 +42,19 @@
 #define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | \
                          EFER_SVME | EFER_LMSLE | EFER_FFXSE)
 
+#define MSR_STAR                        0xc0000081 /* Legacy mode SYSCALL target */
+#define MSR_LSTAR                       0xc0000082 /* Long mode SYSCALL target */
+#define MSR_CSTAR                       0xc0000083 /* Compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK                0xc0000084 /* EFLAGS mask for syscall */
+#define MSR_FS_BASE                     0xc0000100 /* 64bit FS base */
+#define MSR_GS_BASE                     0xc0000101 /* 64bit GS base */
+#define MSR_SHADOW_GS_BASE              0xc0000102 /* SwapGS GS shadow */
+#define MSR_TSC_AUX                     0xc0000103 /* Auxiliary TSC */
+
+/*
+ * Legacy MSR constants in need of cleanup.  No new code below this comment.
+ */
+
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_A_PERFCTR0		0x000004c1
-- 
2.1.4


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