From: Jaeyong Yoo <jaeyong.yoo@samsung.com>
To: Ian Campbell <Ian.Campbell@citrix.com>
Cc: Tim Deegan <tim@xen.org>,
"xen-devel@lists.xen.org" <xen-devel@lists.xen.org>
Subject: Re: [PATCH] ARM: cache coherence problem in guestcopy.c
Date: Tue, 18 Jun 2013 12:05:47 +0000 (GMT) [thread overview]
Message-ID: <17177098.345811371557146762.JavaMail.weblogic@epv6ml06> (raw)
>
> But all of the caches on this platform are PIPT (right?) so isn't it
> actually:
>
> (consumer) (producer)
> xen DomU
> \ / (writing path)
> \ /
> \ /
> (reading path) \ /
> \ /
> (cache)
> ||
> ||
> \/
> _______________________________________
> | mfn | (physical memory)
> ---------------------------------------
>
>
> Or are you saying that the writing path is uncached?
Oops my mistake. As far as I know, it is PIPT and the writing also
should be cached.
>
> I was chatting with Tim and he suggested that the issue might be the
> ReOrder Buffer, which is virtually tagged. In that case a DMB ought to
> be sufficient and not a full cache flush, we think.
>
> We were also speculating that we probably want some DMBs in
> context_switch_{from,to} as well as at return_to_guest.
Actually, I just learned ReOrder Buffer, and it looks like so.
Best,
Jaeyong
next reply other threads:[~2013-06-18 12:05 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-18 12:05 Jaeyong Yoo [this message]
2013-06-18 12:18 ` [PATCH] ARM: cache coherence problem in guestcopy.c Ian Campbell
2013-06-19 15:12 ` Ian Campbell
2013-06-20 11:55 ` Stefano Stabellini
2013-06-20 12:19 ` Tim Deegan
2013-06-25 9:43 ` Ian Campbell
-- strict thread matches above, loose matches on Subject: below --
2013-06-20 8:34 Jaeyong Yoo
2013-06-25 9:22 ` Ian Campbell
2013-07-02 9:38 ` Ian Campbell
2013-07-02 12:14 ` Sengul Thomas
2013-07-02 12:24 ` Sengul Thomas
2013-07-02 12:33 ` Ian Campbell
2013-07-02 12:39 ` Sengul Thomas
2013-06-18 11:22 Jaeyong Yoo
2013-06-18 11:45 ` Ian Campbell
2013-06-18 5:03 Jaeyong Yoo
2013-06-18 9:20 ` Ian Campbell
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