From: Paul Durrant <Paul.Durrant@citrix.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <Andrew.Cooper3@citrix.com>,
"boris.ostrovsky@oracle.com" <boris.ostrovsky@oracle.com>,
Roger Pau Monne <roger.pau@citrix.com>,
Jan Beulich <jbeulich@suse.com>
Subject: Re: [PATCH v5 01/11] x86/pci: introduce hvm_pci_decode_addr
Date: Tue, 22 Aug 2017 11:24:19 +0000 [thread overview]
Message-ID: <1d0748ba16a043efbaa82df8b87adf20@AMSPEX02CL03.citrite.net> (raw)
In-Reply-To: <20170814142850.39133-2-roger.pau@citrix.com>
> -----Original Message-----
> From: Roger Pau Monne [mailto:roger.pau@citrix.com]
> Sent: 14 August 2017 15:29
> To: xen-devel@lists.xenproject.org
> Cc: boris.ostrovsky@oracle.com; konrad.wilk@oracle.com; Roger Pau Monne
> <roger.pau@citrix.com>; Paul Durrant <Paul.Durrant@citrix.com>; Jan
> Beulich <jbeulich@suse.com>; Andrew Cooper
> <Andrew.Cooper3@citrix.com>
> Subject: [PATCH v5 01/11] x86/pci: introduce hvm_pci_decode_addr
>
> And use it in the ioreq code to decode accesses to the PCI IO ports
> into bus, slot, function and register values.
>
> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
> ---
> Cc: Paul Durrant <paul.durrant@citrix.com>
> Cc: Jan Beulich <jbeulich@suse.com>
> Cc: Andrew Cooper <andrew.cooper3@citrix.com>
> ---
> Changes since v4:
> - New in this version.
> ---
> xen/arch/x86/hvm/io.c | 19 +++++++++++++++++++
> xen/arch/x86/hvm/ioreq.c | 12 +++++-------
> xen/include/asm-x86/hvm/io.h | 5 +++++
> 3 files changed, 29 insertions(+), 7 deletions(-)
>
> diff --git a/xen/arch/x86/hvm/io.c b/xen/arch/x86/hvm/io.c
> index 214ab307c4..074cba89da 100644
> --- a/xen/arch/x86/hvm/io.c
> +++ b/xen/arch/x86/hvm/io.c
> @@ -256,6 +256,25 @@ void register_g2m_portio_handler(struct domain
> *d)
> handler->ops = &g2m_portio_ops;
> }
>
> +unsigned int hvm_pci_decode_addr(unsigned int cf8, unsigned int addr,
> + unsigned int *bus, unsigned int *slot,
> + unsigned int *func)
> +{
> + unsigned long bdf;
> +
> + ASSERT(CF8_ENABLED(cf8));
> +
> + bdf = CF8_BDF(cf8);
> + *bus = PCI_BUS(bdf);
> + *slot = PCI_SLOT(bdf);
> + *func = PCI_FUNC(bdf);
> + /*
> + * NB: the lower 2 bits of the register address are fetched from the
> + * offset into the 0xcfc register when reading/writing to it.
> + */
> + return CF8_ADDR_LO(cf8) | (addr & 3);
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c
> index b2a8b0e986..752976d16d 100644
> --- a/xen/arch/x86/hvm/ioreq.c
> +++ b/xen/arch/x86/hvm/ioreq.c
> @@ -1178,18 +1178,16 @@ struct hvm_ioreq_server
> *hvm_select_ioreq_server(struct domain *d,
> CF8_ENABLED(cf8) )
> {
> uint32_t sbdf, x86_fam;
> + unsigned int bus, slot, func, reg;
> +
> + reg = hvm_pci_decode_addr(cf8, p->addr, &bus, &slot, &func);
>
> /* PCI config data cycle */
>
> - sbdf = XEN_DMOP_PCI_SBDF(0,
> - PCI_BUS(CF8_BDF(cf8)),
> - PCI_SLOT(CF8_BDF(cf8)),
> - PCI_FUNC(CF8_BDF(cf8)));
> + sbdf = XEN_DMOP_PCI_SBDF(0, bus, slot, func);
>
> type = XEN_DMOP_IO_RANGE_PCI;
> - addr = ((uint64_t)sbdf << 32) |
> - CF8_ADDR_LO(cf8) |
> - (p->addr & 3);
> + addr = ((uint64_t)sbdf << 32) | reg;
> /* AMD extended configuration space access? */
> if ( CF8_ADDR_HI(cf8) &&
> d->arch.cpuid->x86_vendor == X86_VENDOR_AMD &&
> diff --git a/xen/include/asm-x86/hvm/io.h b/xen/include/asm-x86/hvm/io.h
> index 2484eb1c75..51659b6c7f 100644
> --- a/xen/include/asm-x86/hvm/io.h
> +++ b/xen/include/asm-x86/hvm/io.h
> @@ -149,6 +149,11 @@ void stdvga_deinit(struct domain *d);
>
> extern void hvm_dpci_msi_eoi(struct domain *d, int vector);
>
> +/* Decode a PCI port IO access into a bus/slot/func/reg. */
> +unsigned int hvm_pci_decode_addr(unsigned int cf8, unsigned int addr,
> + unsigned int *bus, unsigned int *slot,
> + unsigned int *func);
> +
> /*
> * HVM port IO handler that performs forwarding of guest IO ports into
> machine
> * IO ports.
> --
> 2.11.0 (Apple Git-81)
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next prev parent reply other threads:[~2017-08-22 11:24 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-14 14:28 [PATCH v5 00/11] vpci: PCI config space emulation Roger Pau Monne
2017-08-14 14:28 ` [PATCH v5 01/11] x86/pci: introduce hvm_pci_decode_addr Roger Pau Monne
2017-08-22 11:24 ` Paul Durrant [this message]
2017-08-24 15:46 ` Jan Beulich
2017-08-25 8:29 ` Roger Pau Monne
2017-08-14 14:28 ` [PATCH v5 02/11] vpci: introduce basic handlers to trap accesses to the PCI config space Roger Pau Monne
2017-08-22 12:05 ` Paul Durrant
2017-09-04 15:38 ` Jan Beulich
2017-09-06 15:40 ` Roger Pau Monné
2017-09-07 9:06 ` Jan Beulich
2017-09-07 11:30 ` Roger Pau Monné
2017-09-07 11:38 ` Jan Beulich
2017-09-08 14:41 ` Roger Pau Monné
2017-09-08 15:56 ` Jan Beulich
2017-09-12 10:42 ` Julien Grall
2017-09-12 10:58 ` Roger Pau Monné
2017-09-12 11:00 ` Julien Grall
2017-08-14 14:28 ` [PATCH v5 03/11] x86/mmcfg: add handlers for the PVH Dom0 MMCFG areas Roger Pau Monne
2017-08-22 12:11 ` Paul Durrant
2017-09-04 15:58 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 04/11] x86/physdev: enable PHYSDEVOP_pci_mmcfg_reserved for PVH Dom0 Roger Pau Monne
2017-09-05 14:57 ` Jan Beulich
2017-09-13 15:55 ` Roger Pau Monné
2017-09-14 9:53 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 05/11] mm: move modify_identity_mmio to global file and drop __init Roger Pau Monne
2017-09-05 15:01 ` Jan Beulich
2017-09-12 7:49 ` Roger Pau Monné
2017-09-12 9:04 ` Jan Beulich
2017-09-12 11:27 ` Roger Pau Monné
2017-09-12 12:53 ` Jan Beulich
2017-09-12 10:53 ` Julien Grall
2017-09-12 11:38 ` Roger Pau Monné
2017-09-12 13:02 ` Julien Grall
2017-08-14 14:28 ` [PATCH v5 06/11] pci: split code to size BARs from pci_add_device Roger Pau Monne
2017-09-05 15:05 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 07/11] pci: add support to size ROM BARs to pci_size_mem_bar Roger Pau Monne
2017-09-05 15:12 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 08/11] vpci/bars: add handlers to map the BARs Roger Pau Monne
2017-09-07 9:53 ` Jan Beulich
2017-09-12 9:54 ` Roger Pau Monné
2017-09-12 10:06 ` Jan Beulich
2017-09-12 11:48 ` Roger Pau Monné
2017-09-12 12:56 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 09/11] vpci/msi: add MSI handlers Roger Pau Monne
2017-08-22 12:20 ` Paul Durrant
2017-09-07 15:29 ` Jan Beulich
2017-09-14 10:08 ` Roger Pau Monné
2017-09-14 10:19 ` Jan Beulich
2017-09-14 10:42 ` Roger Pau Monné
2017-09-14 10:50 ` Jan Beulich
2017-09-14 11:35 ` Roger Pau Monné
2017-09-14 12:09 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 10/11] vpci: add a priority parameter to the vPCI register initializer Roger Pau Monne
2017-09-07 15:32 ` Jan Beulich
2017-08-14 14:28 ` [PATCH v5 11/11] vpci/msix: add MSI-X handlers Roger Pau Monne
2017-09-07 16:11 ` Roger Pau Monné
2017-09-07 16:12 ` Jan Beulich
2017-09-15 10:44 ` Roger Pau Monné
2017-09-15 11:43 ` Jan Beulich
2017-09-15 12:44 ` Roger Pau Monné
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