From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mukesh Rathor Subject: Re: [help] rsp in case of interrupt/exception in ring0 Date: Wed, 24 Feb 2010 20:42:44 -0800 Message-ID: <20100224204244.4baf276e@mantra.us.oracle.com> References: <20100223193957.33c3e13e@mantra.us.oracle.com> <4B84F2E30200007800030ECC@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <4B84F2E30200007800030ECC@vpn.id2.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jan Beulich Cc: "Xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org On Wed, 24 Feb 2010 08:35:31 +0000 "Jan Beulich" wrote: > >>> Mukesh Rathor 24.02.10 04:39 >>> > >When a cpu is in hyp code and int/exception comes in, how/where is > >rsp saved? According to intel manual if there's no ring transition, > >then the cpu doesn't save ss/rsp. > > As you're apparently talking about x86-64, you probably simply read > the wrong (32-bit) part of the manual. On 64-bits, ss:rsp are always > getting saved, no matter whether there's a ring transition. > You are right, few pages later, it talks about 64. Usually, they'll say something about things being different on 64bit. Anyways. I'll email intel docs to fix it... thanks, Mukesh