From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bastian Blank Subject: Re: pvops-2.6.32 - Interrupt routing problem Date: Tue, 23 Mar 2010 13:37:56 +0100 Message-ID: <20100323123756.GA6656@wavehammer.waldi.eu.org> References: <20100315211459.GA9314@wavehammer.waldi.eu.org> <20100316013114.GD7622@phenom.dumpdata.com> <20100316081832.GA20502@wavehammer.waldi.eu.org> <20100316153216.GB28821@phenom.dumpdata.com> <20100316182053.GA2258@wavehammer.waldi.eu.org> <20100319113904.GA29200@wavehammer.waldi.eu.org> <20100319121341.GA30270@wavehammer.waldi.eu.org> <20100321214723.GA29738@wavehammer.waldi.eu.org> <4BA8B62402000078000366E8@vpn.id2.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: <4BA8B62402000078000366E8@vpn.id2.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jan Beulich Cc: Jeremy Fitzhardinge , "xen-devel@lists.xensource.com" , Keir Fraser , Xiantao Zhang , Konrad Rzeszutek Wilk List-Id: xen-devel@lists.xenproject.org On Tue, Mar 23, 2010 at 11:37:56AM +0000, Jan Beulich wrote: > >>> Bastian Blank 21.03.10 22:47 >>> > >Okay, I think I found another problem. Currently the setup looks like > >this: > >- PHYSDEVOP_setup_gsi: set trigger and polarity, unmask pin > Where are you seeing this? Other than Linux' (unmasking edge > triggered IRQs), Xen's io_apic_set_pci_routing() always masks the > entry afaics. In the Linux kernel, xen_register_gsi (arch/x86/xen/pci.c). The io-apic support in Xen is a copy of the Linux code and behaves similar. > >- PHYSDEVOP_map_pirq: map to pirq, set irq handler to guest > >If an interrupt fires between this two calles, what happens? > Since this is only for edge triggered IRQs, I believe the purpose is > to not lose an edge when first enabling the interrupt. No. The interrupt setup is always done before the device setup. This is core kernel functionality. Please explain why you think this is restricted to edge triggered. This is called from the PCI interrupt setup, and usualy used with level triggered interrupts. Bastian -- I have never understood the female capacity to avoid a direct answer to any question. -- Spock, "This Side of Paradise", stardate 3417.3