From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Wang2 Subject: [PATCH 0/4] VPMU: Performance counter virtualization for AMD family 10h processors Date: Wed, 12 May 2010 18:25:02 +0200 Message-ID: <201005121825.02887.wei.wang2@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org Hi, Thist patch set implements performance counter virtualization for AMD famil= y=20 10h processors. Using this patch, profiling tools can be utilized directly= =20 within HVM guest without modification.=20 AMD family 10h processor offers a hardware feature, the Guest Only bit, for= =20 guest profiling. If GO bit is enabled, only guest cycles are counted. This= =20 will highly reduced the complexity of hypervisor design and boost the=20 performance for profiling guest. Thanks, Wei Signed-off-by: Wei Wang =2D-=20 AMD GmbH, Germany Operating System Research Center Legal Information: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34 85609 Dornach b. M=FCnchen Gesch=E4ftsf=FChrer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni Sitz: Dornach, Gemeinde Aschheim, Landkreis M=FCnchen Registergericht M=FCnchen, HRB Nr. 43632