[PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[Kay, Allen M]

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Added additional sleep time between FLR and PCI config restore.



Signed-off-by: Allen Kay <allen.m.kay@intel.com<mailto:allen.m.kay@intel.com>>


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diff -r 370fd9f97c70 tools/python/xen/util/pci.py
--- a/tools/python/xen/util/pci.py	Sat May 22 07:18:16 2010 +0100
+++ b/tools/python/xen/util/pci.py	Thu Jun 03 11:42:05 2010 -0700
@@ -523,6 +523,7 @@
     return (pci_list, cfg_list)
 
 def restore_pci_conf_space(pci_cfg_list):
+    time.sleep(1.0)
     pci_list = pci_cfg_list[0]
     cfg_list = pci_cfg_list[1]
     for i in range(0, len(pci_list)):

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Re: [PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[Jean Guyader]

On 4 June 2010 01:22, Kay, Allen M <allen.m.kay@intel.com> wrote:
> Added additional sleep time between FLR and PCI config restore.
>
>
>
> Signed-off-by: Allen Kay <allen.m.kay@intel.com>
>

Yes, to take more time to do an FLR on those platform, but I don't think
this is a proper fix. The fix we have for that in our tree (XCI) is to make
sure the value we write when we restore the pci config space stick in
pciback.

I'll send the patch later today,
Jean

RE: [PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[Kay, Allen M]

That's a more robust fix.  Thanks.

Allen

-----Original Message-----
From: Jean Guyader [mailto:jean.guyader@gmail.com] 
Sent: Friday, June 04, 2010 1:54 AM
To: Kay, Allen M
Cc: xen-devel@lists.xensource.com; ian.pratt@eu.citrix.com; Han, Weidong; Ross.Philipson@citrix.com; jean.guyader@citrix.com
Subject: Re: [Xen-devel] [PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

On 4 June 2010 01:22, Kay, Allen M <allen.m.kay@intel.com> wrote:
> Added additional sleep time between FLR and PCI config restore.
>
>
>
> Signed-off-by: Allen Kay <allen.m.kay@intel.com>
>

Yes, to take more time to do an FLR on those platform, but I don't think
this is a proper fix. The fix we have for that in our tree (XCI) is to make
sure the value we write when we restore the pci config space stick in
pciback.

I'll send the patch later today,
Jean

Re: [PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[Konrad Rzeszutek Wilk]

> Yes, to take more time to do an FLR on those platform, but I don't think
> this is a proper fix. The fix we have for that in our tree (XCI) is to make
> sure the value we write when we restore the pci config space stick in
> pciback.
> 
> I'll send the patch later today,

Please send it to me as well so I can stick in the proper pv-ops tree.

Re: [PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[Jean Guyader]

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On Fri, Jun 04, 2010 at 09:30:40PM +0100, Konrad Rzeszutek Wilk wrote:
> > Yes, to take more time to do an FLR on those platform, but I don't think
> > this is a proper fix. The fix we have for that in our tree (XCI) is to make
> > sure the value we write when we restore the pci config space stick in
> > pciback.
> > 
> > I'll send the patch later today,
> 
> Please send it to me as well so I can stick in the proper pv-ops tree.

Thanks Konrad.

Here is the patch for a 2.6.27 kernel.

pciback: Verify write when restoring the pci config space after FLR

Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com>

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diff --git a/drivers/xen/pciback/pciback_ops.c b/drivers/xen/pciback/pciback_ops.c
index 2b77b31..62267e3 100644
--- a/drivers/xen/pciback/pciback_ops.c
+++ b/drivers/xen/pciback/pciback_ops.c
@@ -56,11 +56,20 @@ void pciback_reload_config_space(struct pci_dev *dev)
 	struct pciback_dev_data *dev_data = pci_get_drvdata(dev);
 	u32 *ptr = (u32*)dev_data->cfg_space;
 	int i, val, count = dev->cfg_size/sizeof(u32);
+        int limit = 0;
 
 	for (i = 0; i < count; i += sizeof(u32), ptr++) {
 		pci_read_config_dword(dev, i, &val);
-		if (val != *ptr)
+		while (limit < 1000 && val != *ptr)
+                {
 			pci_write_config_dword(dev, i, *ptr);
+                        pci_read_config_dword(dev, i, &val);
+                        mdelay(1);
+                        limit++;
+                }
+                if (limit == 1000)
+                    printk(KERN_ERR "pciback: Error reloading config space after flr dev:%x offset:%x\n",
+                            dev->devfn, i);
 	}
 }
 

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Re: [PATCH][VTD] fixed a timing issue on DELL calpella laptop while doing graphics pass-through

[Konrad Rzeszutek Wilk]

On Sat, Jun 05, 2010 at 09:40:10AM +0100, Jean Guyader wrote:
> On Fri, Jun 04, 2010 at 09:30:40PM +0100, Konrad Rzeszutek Wilk wrote:
> > > Yes, to take more time to do an FLR on those platform, but I don't think
> > > this is a proper fix. The fix we have for that in our tree (XCI) is to make
> > > sure the value we write when we restore the pci config space stick in
> > > pciback.
> > > 
> > > I'll send the patch later today,
> > 
> > Please send it to me as well so I can stick in the proper pv-ops tree.
> 
> Thanks Konrad.
> 
> Here is the patch for a 2.6.27 kernel.

I seem to be missing a wealth of previous checkins. There is no 
pciback_reload_config_space in the pciback code that I pulled from
2.6.18.

If you could re-base against Jeremy's PV-OPS kernel and send those
patches that would be tremendously helpful.

Here is a Wiki that explains in detail how to get the PV-OPS kernel and
build it: http://wiki.xensource.com/xenwiki/XenParavirtOps

Much appreciated!
> 
> pciback: Verify write when restoring the pci config space after FLR
> 
> Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com>

> diff --git a/drivers/xen/pciback/pciback_ops.c b/drivers/xen/pciback/pciback_ops.c
> index 2b77b31..62267e3 100644
> --- a/drivers/xen/pciback/pciback_ops.c
> +++ b/drivers/xen/pciback/pciback_ops.c
> @@ -56,11 +56,20 @@ void pciback_reload_config_space(struct pci_dev *dev)
>  	struct pciback_dev_data *dev_data = pci_get_drvdata(dev);
>  	u32 *ptr = (u32*)dev_data->cfg_space;
>  	int i, val, count = dev->cfg_size/sizeof(u32);
> +        int limit = 0;
>  
>  	for (i = 0; i < count; i += sizeof(u32), ptr++) {
>  		pci_read_config_dword(dev, i, &val);
> -		if (val != *ptr)
> +		while (limit < 1000 && val != *ptr)
> +                {
>  			pci_write_config_dword(dev, i, *ptr);
> +                        pci_read_config_dword(dev, i, &val);
> +                        mdelay(1);
> +                        limit++;
> +                }
> +                if (limit == 1000)
> +                    printk(KERN_ERR "pciback: Error reloading config space after flr dev:%x offset:%x\n",
> +                            dev->devfn, i);
>  	}
>  }
>