From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sheng Yang Subject: [PATCH] C6 state with EOI issue fix for some Intel processors Date: Wed, 15 Sep 2010 15:10:43 +0800 Message-ID: <201009151510.44090.sheng@linux.intel.com> Mime-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_0FHkMbq7lMjEVVo" Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Keir Fraser Cc: "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org --Boundary-00=_0FHkMbq7lMjEVVo Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit There is an errata in some of Intel processors. AAJ72. EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine If core C6 is entered after the start of an interrupt service routine but before a write to the APIC EOI register, the core may not send an EOI transaction (if needed) and further interrupts from the same priority level or lower may be blocked. This patch fix this issue, by checking if ISR is pending before enter deep Cx state. If so, it would use power->safe_state instead of deep Cx state to prevent the above issue happen. --Boundary-00=_0FHkMbq7lMjEVVo Content-Type: text/x-patch; charset="UTF-8"; name="c6_eoi_fix.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="c6_eoi_fix.patch" diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -367,6 +367,28 @@ return atomic_read(&this_cpu(schedule_data).urgent_count); } +static int cpu_has_isr_pending(void) +{ + int i; + + for ( i = 1; i < 8; i++ ) + if ( apic_read(APIC_ISR + (i << 4)) != 0 ) + return 1; + return 0; +} + +int errata_c6_eoi_fix_needed(void) +{ + int model = boot_cpu_data.x86_model; + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && + boot_cpu_data.x86 == 6 && + ((model == 0x1a || model == 0x1e || model == 0x1f || + model == 0x25 || model == 0x2c || model == 0x2f) && + !directed_eoi_enabled) ) + return 1; + return 0; +} + static void acpi_processor_idle(void) { struct acpi_processor_power *power = processor_powers[smp_processor_id()]; @@ -417,6 +439,16 @@ return; } + /* + * There was an errata with some Core i7 processors that, EOI + * transaction may not be sent if software enters core C6 during an + * interrupt service routine. So we don't want to get into deep Cx + * state if there was isr pending. + */ + if ( cpu_has_apic && errata_c6_eoi_fix_needed() && + cx->type == ACPI_STATE_C3 && cpu_has_isr_pending() ) + cx = power->safe_state; + power->last_state = cx; /* --Boundary-00=_0FHkMbq7lMjEVVo Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel --Boundary-00=_0FHkMbq7lMjEVVo--