From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sheng Yang Subject: Re: [PATCH] C6 state with EOI issue fix for some Intel processors Date: Wed, 15 Sep 2010 15:18:50 +0800 Message-ID: <201009151518.50179.sheng@linux.intel.com> References: <201009151510.44090.sheng@linux.intel.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <201009151510.44090.sheng@linux.intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: xen-devel@lists.xensource.com Cc: Keir Fraser List-Id: xen-devel@lists.xenproject.org On Wednesday 15 September 2010 15:10:43 Sheng Yang wrote: > There is an errata in some of Intel processors. > > AAJ72. EOI Transaction May Not be Sent if Software Enters Core C6 During > an Interrupt Service Routine > > If core C6 is entered after the start of an interrupt service routine but > before a write to the APIC EOI register, the core may not send an EOI > transaction (if needed) and further interrupts from the same priority > level or lower may be blocked. > > This patch fix this issue, by checking if ISR is pending before enter deep > Cx state. If so, it would use power->safe_state instead of deep Cx state > to prevent the above issue happen. Signed-off-by: Sheng Yang -- regards Yang, Sheng