From: Wei Wang2 <wei.wang2@amd.com>
To: Jan Beulich <jbeulich@novell.com>
Cc: "Huang2, Wei" <Wei.Huang2@amd.com>,
Boris Ostrovsky <boris.ostrovsky@amd.com>,
"xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
Subject: [PATCH] AMD IOMMU: Fix an interrupt remapping issue
Date: Fri, 8 Apr 2011 12:52:04 +0200 [thread overview]
Message-ID: <201104081252.04840.wei.wang2@amd.com> (raw)
Some device could generate bogus interrupts if an IO-APIC RTE and an iommu
interrupt remapping entry are not consistent during 2 adjacent 64bits IO-APIC
RTE updates. For example, if the 2nd operation updates destination bits in
RTE for SATA device and unmask it, in some case, SATA device will assert
ioapic pin to generate interrupt immediately using new destination but iommu
could still translate it into the old destination, then dom0 would be
confused. To fix that, we sync up interrupt remapping entry with IO-APIC IRE
on every 32 bits operation and foward IOAPIC RTE updates after interrupt
remapping table has been changed.
Jan, This patch fixes SATA device issue we observed (Bug #680824), please
review it. Thanks!
Wei
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Advanced Micro Devices GmbH
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next reply other threads:[~2011-04-08 10:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-08 10:52 Wei Wang2 [this message]
2011-04-08 11:26 ` [PATCH] AMD IOMMU: Fix an interrupt remapping issue Jan Beulich
-- strict thread matches above, loose matches on Subject: below --
2011-04-08 11:35 Wei Wang2
2011-04-08 13:43 ` Jan Beulich
2011-04-08 14:26 ` Wei Wang2
2011-04-08 14:39 ` Jan Beulich
2011-04-08 15:06 ` Wei Wang2
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