From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Wang2 Subject: [PATCH] AMD IOMMU: Fix an interrupt remapping issue Date: Fri, 8 Apr 2011 12:52:04 +0200 Message-ID: <201104081252.04840.wei.wang2@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xensource.com Errors-To: xen-devel-bounces@lists.xensource.com To: Jan Beulich Cc: "Huang2, Wei" , Boris Ostrovsky , "xen-devel@lists.xensource.com" List-Id: xen-devel@lists.xenproject.org Some device could generate bogus interrupts if an IO-APIC RTE and an iommu= =20 interrupt remapping entry are not consistent during 2 adjacent 64bits IO-AP= IC=20 RTE updates. For example, if the 2nd operation updates destination bits in= =20 RTE for SATA device and unmask it, in some case, SATA device will assert=20 ioapic pin to generate interrupt immediately using new destination but iomm= u=20 could still translate it into the old destination, then dom0 would be=20 confused. To fix that, we sync up interrupt remapping entry with IO-APIC IR= E=20 on every 32 bits operation and foward IOAPIC RTE updates after interrupt=20 remapping table has been changed.=20 Jan, This patch fixes SATA device issue we observed (Bug #680824), please=20 review it. Thanks!=20 Wei =2D- Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim,=20 Landkreis M=FCnchen Registergericht M=FCnchen,=20 HRB Nr. 43632 WEEE-Reg-Nr: DE 12919551 Gesch=E4ftsf=FChrer: Alberto Bozzo, Andrew Bowd