From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tim Deegan Subject: Re: [PATCH 03 of 10] arm: Move some GIC distributor init out of the per-CPU init function Date: Mon, 27 Feb 2012 19:30:59 +0000 Message-ID: <20120227193059.GD98737@ocelot.phlegethon.org> References: <437ad1207a175c9ad376.1330018850@whitby.uk.xensource.com> <1330363933.8557.317.camel@zakaz.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1330363933.8557.317.camel@zakaz.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: "xen-devel@lists.xensource.com" , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org At 17:32 +0000 on 27 Feb (1330363933), Ian Campbell wrote: > On Thu, 2012-02-23 at 17:40 +0000, Tim Deegan wrote: > > # HG changeset patch > > # User Tim Deegan > > # Date 1330018799 0 > > # Node ID 437ad1207a175c9ad376871f3f4c075dbcd5b6e6 > > # Parent ec051056db2b6d37344629e2f01d17240099d5ec > > arm: Move some GIC distributor init out of the per-CPU init function > > > > Signed-off-by: Tim Deegan > > > > diff -r ec051056db2b -r 437ad1207a17 xen/arch/arm/gic.c > > --- a/xen/arch/arm/gic.c Thu Feb 23 17:39:59 2012 +0000 > > +++ b/xen/arch/arm/gic.c Thu Feb 23 17:39:59 2012 +0000 > > @@ -216,14 +216,6 @@ static void __init gic_dist_init(void) > > for ( i = 32; i < gic.lines; i += 32 ) > > GICD[GICD_ICENABLER + i / 32] = ~0ul; > > > > - /* Turn on the distributor */ > > - GICD[GICD_CTLR] = GICD_CTL_ENABLE; > > -} > > - > > -static void __cpuinit gic_cpu_init(void) > > -{ > > - int i; > > - > > /* Disable all PPI and enable all SGI */ > > GICD[GICD_ICENABLER] = 0xffff0000; /* Disable all PPI */ > > GICD[GICD_ISENABLER] = 0x0000ffff; /* Enable all SGI */ > > PPIs and SGIs are per physical-CPU and therefore, I think, the GICD > registers of various sorts which refer to the first 32 interrupts are > per physical-CPU as well. IOW moving these from gic_cpu_init to > gic_dist_init is wrong? Yep, you're right ISENABLER0 and ICENABLER0 are banked. I'll replace this with a comment explaining that. Cheers, Tim.