From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tim Deegan <tim@xen.org>
Subject: Re: [PATCH 3 of 3] x86/mm: Enable paging and sharing in
	AMD NPT mode
Date: Thu, 8 Mar 2012 13:30:21 +0000
Message-ID: <20120308133021.GI64337@ocelot.phlegethon.org>
References: <patchbomb.1330571755@xdev.gridcentric.ca>
	<4c6bee5a191a2325be96.1330571758@xdev.gridcentric.ca>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <xen-devel-bounces@lists.xen.org>
Content-Disposition: inline
In-Reply-To: <4c6bee5a191a2325be96.1330571758@xdev.gridcentric.ca>
List-Unsubscribe: <http://lists.xen.org/cgi-bin/mailman/options/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=unsubscribe>
List-Post: <mailto:xen-devel@lists.xen.org>
List-Help: <mailto:xen-devel-request@lists.xen.org?subject=help>
List-Subscribe: <http://lists.xen.org/cgi-bin/mailman/listinfo/xen-devel>,
	<mailto:xen-devel-request@lists.xen.org?subject=subscribe>
Sender: xen-devel-bounces@lists.xen.org
Errors-To: xen-devel-bounces@lists.xen.org
To: Andres Lagar-Cavilla <andres@lagarcavilla.org>
Cc: olaf@aepfle.de, xen-devel@lists.xensource.com, andres@gridcentric.ca, wei.wang2@amd.com, hongkaixing@huawei.com, adin@gridcentric.ca
List-Id: xen-devel@lists.xenproject.org

At 22:15 -0500 on 29 Feb (1330553758), Andres Lagar-Cavilla wrote:
>  xen/arch/x86/mm/mem_event.c   |  7 +++++--
>  xen/arch/x86/mm/mem_sharing.c |  7 +++++++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> 
> Both features are mutually exclusive with sharing iommu and p2m tables.
> 
> Signed-off-by: Andres Lagar-Cavilla <andres@lagarcavilla.org>
> Signed-off-by: Adin Scannell <adin@scannell.ca>
> 
> diff -r d6c3c77ad749 -r 4c6bee5a191a xen/arch/x86/mm/mem_event.c
> --- a/xen/arch/x86/mm/mem_event.c
> +++ b/xen/arch/x86/mm/mem_event.c
> @@ -550,8 +550,11 @@ int mem_event_domctl(struct domain *d, x
>              if ( !hap_enabled(d) )
>                  break;
>  
> -            /* Currently only EPT is supported */
> -            if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
> +            /* Currently EPT or AMD with no iommu/hap page table sharing are
> +             * supported */
> +            if ( !((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) ||
> +                   ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && 
> +                     !iommu_hap_pt_share)) )

AFAICT p2m tricks are not going to work with IOMMU/passthrough at all,
since there's no mechanism to fault and retry.  So the interlock should
really be against need_iommu() or similar.  (And vice versa, to stop a
device being passed through to a VM that has sharing/paging/events
enabled).

Cheers,

Tim