From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tim Deegan Subject: Re: [PATCH 29/38] arm: delay enabling data-cache until paging enabled. Date: Thu, 7 Jun 2012 14:59:30 +0100 Message-ID: <20120607135930.GW70339@ocelot.phlegethon.org> References: <1338565113.17466.141.camel@zakaz.uk.xensource.com> <1338565207-2888-1-git-send-email-ian.campbell@citrix.com> <1338565207-2888-29-git-send-email-ian.campbell@citrix.com> <20120601170514.GD77921@ocelot.phlegethon.org> <1338577461.14877.61.camel@dagon.hellion.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1338577461.14877.61.camel@dagon.hellion.org.uk> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org At 20:04 +0100 on 01 Jun (1338581061), Ian Campbell wrote: > On Fri, 2012-06-01 at 18:05 +0100, Tim Deegan wrote: > > At 15:39 +0000 on 01 Jun (1338565198), Ian Campbell wrote: > > > With enough warnings enabled the model seemed to be complaining that pages > > > cached before paging was enabled had been mapped with to inconsistent sets of > > > attributes. I'm not convinced that isn't a model issue, nor am I convinced > > > this has really fixed anything, but it seems sensible enough. > > > > This might be what breaks secondary CPU bringup: pagetables built by CPU > > 0 may not have been flushed all the way to RAM when CPU 1 comes up, and > > CPU 1 isn't participating in cache coherence protocols when it > > starts to need them. > > The issue here is the lack of the necessary flush, rather than this > change particularly, right? It turns out to be much more prosaic - the patch to delete the identity mapping from the boot pagetables was scuppering non-boot CPUs. So this is OK, but can I suggest this to tidy it up? diff --git a/xen/arch/arm/head.S b/xen/arch/arm/head.S index 71197af..0d8ce0f 100644 --- a/xen/arch/arm/head.S +++ b/xen/arch/arm/head.S @@ -211,17 +211,13 @@ pt_ready: ldr r1, =paging /* Explicit vaddr, not RIP-relative */ mrc CP32(r0, HSCTLR) - orr r0, r0, #0x1 /* Add in the MMU enable bit */ + orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */ dsb /* Flush PTE writes and finish reads */ mcr CP32(r0, HSCTLR) /* now paging is enabled */ isb /* Now, flush the icache */ mov pc, r1 /* Get a proper vaddr into PC */ paging: - mrc CP32(r0, HSCTLR) /* Now enable data cache */ - orr r0, r0, #(SCTLR_C) - mcr CP32(r0, HSCTLR) - #ifdef EARLY_UART_ADDRESS /* Recover the UART address in the new address space. */ lsl r11, #11