From mboxrd@z Thu Jan  1 00:00:00 1970
From: Tim Deegan <tim@xen.org>
Subject: Re: [PATCH 6/7] xen/arm: flush D-cache and I-cache when
	appropriate
Date: Sat, 27 Oct 2012 12:54:23 +0100
Message-ID: <20121027115423.GA90857@ocelot.phlegethon.org>
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At 11:44 +0100 on 27 Oct (1351338268), Tim Deegan wrote:
>  /* Function for flushing medium-sized areas.
>   * if 'range' is large enough we might want to use model-specific
>   * full-cache flushes. */
>  static inline void flush_xen_dcache_va_range(void *p, unsigned long size)
>  {
>      void *end;
>      unsigned long cacheline_bytes = READ_CP32(CCSIDR);
>      barrier();       /* So the compiler issues all writes to the range */
>      dsb();           /* So the CPU issues all writes to the range */ 

Oh - I just noticed that the way we've defined dsb() it includes a
memory clobber.   So I guess we don't need barrier() as well there.

We might want to look at the other users of dsb() and see if we want to
drop the memory clobber from it as well.  But OTOH we may be getting
way into premature optimization already. :)

Tim.