[PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Chen Baozi]

Signed-off-by: Chen Baozi <baozich@gmail.com>
---
 xen/arch/arm/arm32/mode_switch.S      | 34 +++++++++++++++++++++++++++++++---
 xen/include/asm-arm/platforms/omap5.h | 17 +++++++++++++++++
 2 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S
index 3500eb0..e86d3d1 100644
--- a/xen/arch/arm/arm32/mode_switch.S
+++ b/xen/arch/arm/arm32/mode_switch.S
@@ -21,11 +21,13 @@
 #include <asm/page.h>
 #include <asm/platforms/vexpress.h>
 #include <asm/platforms/exynos5.h>
+#include <asm/platforms/omap5.h>
 #include <asm/asm_defns.h>
 #include <asm/gic.h>
 
 /* Wake up secondary cpus
- * This code relies on Machine ID and only works for Vexpress and the Arndale
+ * This code relies on Machine ID and only works for Vexpress, the Arndale
+ * and the OMAP5 uEVM.
  * TODO: Move this code either later (via platform specific desc) or in a bootwrapper
  * r5: Machine ID
  * Clobber r0 r2 */
@@ -34,6 +36,10 @@ kick_cpus:
         ldr   r0, =MACH_TYPE_SMDK5250
         teq   r5, r0                          /* Are we running on the arndale? */
         beq   kick_cpus_arndale
+	/* for OMAP5432 */
+	ldr   r0, =MACH_TYPE_OMAP5_SEVM
+	teq   r5, r0
+	beq   kick_cpus_omap5
         /* otherwise versatile express */
         /* write start paddr to v2m sysreg FLAGSSET register */
         ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO address */
@@ -55,6 +61,20 @@ kick_cpus_arndale:
         str   r2, [r0]
         dsb
         ldr   r2, =EXYNOS5_GIC_BASE_ADDRESS   /* r2 := Exynos5 gic base address */
+	b     kick_cpus_sgi
+kick_cpus_omap5:
+	/* write start paddr to AuxCoreBoot1 where ROM code will jump */
+        ldr   r0, =(OMAP_AUX_CORE_BOOT_1)
+        ldr   r2, =start
+        add   r2, r2, r10
+        str   r2, [r0]
+        ldr   r0, =(OMAP_AUX_CORE_BOOT_0)
+        mov   r2, #0x20
+        str   r2, [r0]
+        dsb
+        sev
+        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
+        b     kick_cpus_sgi
 kick_cpus_sgi:
         /* send an interrupt */
         ldr   r0, =GIC_DR_OFFSET              /* GIC distributor offset */
@@ -90,15 +110,23 @@ enter_hyp_mode:
         bic   r0, r0, #0xe           /* Clear EA, FIQ and IRQ */
         mcr   CP32(r0, SCR)
 
-        ldr   r2, =MACH_TYPE_SMDK5250   /* r4 := Arndale machine ID */
         /* By default load Arndale defaults values */
+        ldr   r2, =MACH_TYPE_SMDK5250       /* r2 := Arndale machine ID */
         ldr   r0, =EXYNOS5_TIMER_FREQUENCY  /* r0 := timer's frequency */
         ldr   r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */
-        /* If it's not the Arndale machine ID, load VE values */
         teq   r5, r2
+        beq   1f
+        /* If it's not the Arndale machine ID, try OMAP5 uEVM */
+        ldr   r2, =MACH_TYPE_OMAP5_SEVM     /* r2 := OMAP5 uEVM machine ID */
+        ldr   r0, =OMAP5_TIMER_FREQUENCY    /* r0 := timer's frequency */
+        ldr   r1, =OMAP5_GIC_BASE_ADDRESS   /* r1 := GIC base address */
+        teq   r5, r2
+        beq   1f
+        /* If it's not the OMAP5432 machine ID, load VE values */
         ldrne r0, =V2M_TIMER_FREQUENCY
         ldrne r1, =V2M_GIC_BASE_ADDRESS
 
+1:
         /* Ugly: the system timer's frequency register is only
          * programmable in Secure state.  Since we don't know where its
          * memory-mapped control registers live, we can't find out the
diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h
index 092f340..a8b0937 100644
--- a/xen/include/asm-arm/platforms/omap5.h
+++ b/xen/include/asm-arm/platforms/omap5.h
@@ -13,6 +13,23 @@
 #define OMAP5_CM_CLKSEL_SYS                     0x10
 #define SYS_CLKSEL_MASK                         0xfffffff8
 
+#define OMAP_AUX_CORE_BOOT_0                    0x48281800
+#define OMAP_AUX_CORE_BOOT_1                    0x48281804
+
+/* Constants below is only used in assembly because the DTS is not yet parsed */
+#ifdef __ASSEMBLY__
+
+/* GIC Base Address */
+#define OMAP5_GIC_BASE_ADDRESS                  0x48210000
+
+/* Timer's frequency */
+#define OMAP5_TIMER_FREQUENCY                   6144000 /*  6.144 Mhz */
+
+/* OMAP5432 uEVM machine ID */
+#define MACH_TYPE_OMAP5_SEVM                    3777
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_ARM_PLATFORMS_OMAP5_H */
 
 /*
-- 
1.8.1.4

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Tim Deegan]

At 17:16 +0800 on 15 Aug (1376587012), Chen Baozi wrote:
> @@ -34,6 +36,10 @@ kick_cpus:
>          ldr   r0, =MACH_TYPE_SMDK5250
>          teq   r5, r0                          /* Are we running on the arndale? */
>          beq   kick_cpus_arndale
> +	/* for OMAP5432 */
> +	ldr   r0, =MACH_TYPE_OMAP5_SEVM
> +	teq   r5, r0
> +	beq   kick_cpus_omap5

There are some hard tabs here.

Tim.

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Andrii Anisov]

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Chen,

Could you please explain how this code switches to hyp mode?
I do not see related code.

*Sincerely,*
*Andrii Anisov.*

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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Chen Baozi]

On Aug 15, 2013, at 5:34 PM, Andrii Anisov <andrii.anisov@globallogic.com> wrote:

> Chen,
> 
> Could you please explain how this code switches to hyp mode?
> I do not see related code.

The actual mode switch codes is in the end of mode_switch.s：

	mrs	r0, cpsr	/* Copy the CPSR */
	add	r0, r0, #0x4	/* 0x16 (Monitor) -> 0x1a (Hyp) */
	msr	spsr_cxsf, r0	/* into the SPSR */

Hmmm, I think my patch name should be more accurate. It mainly added
OMAP5 support in "enter_hyp_mode" routine, which actually makes it
set cntfrq of arch_timer properly in secure mode.

Cheers,

Baozi


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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Julien Grall]

On 15 August 2013 10:16, Chen Baozi <baozich@gmail.com> wrote:
>
> Signed-off-by: Chen Baozi <baozich@gmail.com>
> ---
>  xen/arch/arm/arm32/mode_switch.S      | 34 +++++++++++++++++++++++++++++++---
>  xen/include/asm-arm/platforms/omap5.h | 17 +++++++++++++++++
>  2 files changed, 48 insertions(+), 3 deletions(-)
>
> diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S
> index 3500eb0..e86d3d1 100644
> --- a/xen/arch/arm/arm32/mode_switch.S
> +++ b/xen/arch/arm/arm32/mode_switch.S
> @@ -21,11 +21,13 @@
>  #include <asm/page.h>
>  #include <asm/platforms/vexpress.h>
>  #include <asm/platforms/exynos5.h>
> +#include <asm/platforms/omap5.h>
>  #include <asm/asm_defns.h>
>  #include <asm/gic.h>
>
>  /* Wake up secondary cpus
> - * This code relies on Machine ID and only works for Vexpress and the Arndale
> + * This code relies on Machine ID and only works for Vexpress, the Arndale
> + * and the OMAP5 uEVM.
>   * TODO: Move this code either later (via platform specific desc) or in a bootwrapper
>   * r5: Machine ID
>   * Clobber r0 r2 */
> @@ -34,6 +36,10 @@ kick_cpus:
>          ldr   r0, =MACH_TYPE_SMDK5250
>          teq   r5, r0                          /* Are we running on the arndale? */
>          beq   kick_cpus_arndale
> +       /* for OMAP5432 */
> +       ldr   r0, =MACH_TYPE_OMAP5_SEVM
> +       teq   r5, r0
> +       beq   kick_cpus_omap5
>          /* otherwise versatile express */
>          /* write start paddr to v2m sysreg FLAGSSET register */
>          ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO address */
> @@ -55,6 +61,20 @@ kick_cpus_arndale:
>          str   r2, [r0]
>          dsb
>          ldr   r2, =EXYNOS5_GIC_BASE_ADDRESS   /* r2 := Exynos5 gic base address */
> +       b     kick_cpus_sgi
> +kick_cpus_omap5:
> +       /* write start paddr to AuxCoreBoot1 where ROM code will jump */
> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_1)
> +        ldr   r2, =start
> +        add   r2, r2, r10
> +        str   r2, [r0]
> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_0)
> +        mov   r2, #0x20
> +        str   r2, [r0]
> +        dsb
> +        sev
> +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
> +        b     kick_cpus_sgi
>  kick_cpus_sgi:
>          /* send an interrupt */
>          ldr   r0, =GIC_DR_OFFSET              /* GIC distributor offset */
> @@ -90,15 +110,23 @@ enter_hyp_mode:
>          bic   r0, r0, #0xe           /* Clear EA, FIQ and IRQ */
>          mcr   CP32(r0, SCR)
>
> -        ldr   r2, =MACH_TYPE_SMDK5250   /* r4 := Arndale machine ID */
>          /* By default load Arndale defaults values */
> +        ldr   r2, =MACH_TYPE_SMDK5250       /* r2 := Arndale machine ID */
>          ldr   r0, =EXYNOS5_TIMER_FREQUENCY  /* r0 := timer's frequency */
>          ldr   r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */
> -        /* If it's not the Arndale machine ID, load VE values */
>          teq   r5, r2
> +        beq   1f
> +        /* If it's not the Arndale machine ID, try OMAP5 uEVM */
> +        ldr   r2, =MACH_TYPE_OMAP5_SEVM     /* r2 := OMAP5 uEVM machine ID */
> +        ldr   r0, =OMAP5_TIMER_FREQUENCY    /* r0 := timer's frequency */
> +        ldr   r1, =OMAP5_GIC_BASE_ADDRESS   /* r1 := GIC base address */
> +        teq   r5, r2
> +        beq   1f
> +        /* If it's not the OMAP5432 machine ID, load VE values */
>          ldrne r0, =V2M_TIMER_FREQUENCY
>          ldrne r1, =V2M_GIC_BASE_ADDRESS
>
> +1:
>          /* Ugly: the system timer's frequency register is only
>           * programmable in Secure state.  Since we don't know where its
>           * memory-mapped control registers live, we can't find out the

I'm not in favor to extend this assembly file (see full explanation on
Ian's mail http://lists.xen.org/archives/html/xen-devel/2013-06/msg01231.html).

Some ideas to remove this file:
   - Move kick cpus code later (ie in C code) and per platform
   - Use U-boot or a bootwrapper to switch CPUs to HYP mode

Cheers,

-- 
Julien Grall

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Andrii Anisov]

[-- Attachment #1.1: Type: text/plain, Size: 581 bytes --]

>
>
> The actual mode switch codes is in the end of mode_switch.s：
>
>         mrs     r0, cpsr        /* Copy the CPSR */
>         add     r0, r0, #0x4    /* 0x16 (Monitor) -> 0x1a (Hyp) */
>         msr     spsr_cxsf, r0   /* into the SPSR */
>
> Hmmm, I think my patch name should be more accurate. It mainly added
> OMAP5 support in "enter_hyp_mode" routine, which actually makes it
> set cntfrq of arch_timer properly in secure mode.
>
> Cheers,
>
> Baozi
>

I'm really surprised you have got CPU1 in Secure Supervisor mode.

Sincerely,
Andrii Anisov.

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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Chen Baozi]

On Aug 15, 2013, at 6:03 PM, Julien Grall <julien.grall@linaro.org> wrote:

> On 15 August 2013 10:16, Chen Baozi <baozich@gmail.com> wrote:
>> 
>> Signed-off-by: Chen Baozi <baozich@gmail.com>
>> ---
>> xen/arch/arm/arm32/mode_switch.S      | 34 +++++++++++++++++++++++++++++++---
>> xen/include/asm-arm/platforms/omap5.h | 17 +++++++++++++++++
>> 2 files changed, 48 insertions(+), 3 deletions(-)
>> 
>> diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S
>> index 3500eb0..e86d3d1 100644
>> --- a/xen/arch/arm/arm32/mode_switch.S
>> +++ b/xen/arch/arm/arm32/mode_switch.S
>> @@ -21,11 +21,13 @@
>> #include <asm/page.h>
>> #include <asm/platforms/vexpress.h>
>> #include <asm/platforms/exynos5.h>
>> +#include <asm/platforms/omap5.h>
>> #include <asm/asm_defns.h>
>> #include <asm/gic.h>
>> 
>> /* Wake up secondary cpus
>> - * This code relies on Machine ID and only works for Vexpress and the Arndale
>> + * This code relies on Machine ID and only works for Vexpress, the Arndale
>> + * and the OMAP5 uEVM.
>>  * TODO: Move this code either later (via platform specific desc) or in a bootwrapper
>>  * r5: Machine ID
>>  * Clobber r0 r2 */
>> @@ -34,6 +36,10 @@ kick_cpus:
>>         ldr   r0, =MACH_TYPE_SMDK5250
>>         teq   r5, r0                          /* Are we running on the arndale? */
>>         beq   kick_cpus_arndale
>> +       /* for OMAP5432 */
>> +       ldr   r0, =MACH_TYPE_OMAP5_SEVM
>> +       teq   r5, r0
>> +       beq   kick_cpus_omap5
>>         /* otherwise versatile express */
>>         /* write start paddr to v2m sysreg FLAGSSET register */
>>         ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO address */
>> @@ -55,6 +61,20 @@ kick_cpus_arndale:
>>         str   r2, [r0]
>>         dsb
>>         ldr   r2, =EXYNOS5_GIC_BASE_ADDRESS   /* r2 := Exynos5 gic base address */
>> +       b     kick_cpus_sgi
>> +kick_cpus_omap5:
>> +       /* write start paddr to AuxCoreBoot1 where ROM code will jump */
>> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_1)
>> +        ldr   r2, =start
>> +        add   r2, r2, r10
>> +        str   r2, [r0]
>> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_0)
>> +        mov   r2, #0x20
>> +        str   r2, [r0]
>> +        dsb
>> +        sev
>> +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
>> +        b     kick_cpus_sgi
>> kick_cpus_sgi:
>>         /* send an interrupt */
>>         ldr   r0, =GIC_DR_OFFSET              /* GIC distributor offset */
>> @@ -90,15 +110,23 @@ enter_hyp_mode:
>>         bic   r0, r0, #0xe           /* Clear EA, FIQ and IRQ */
>>         mcr   CP32(r0, SCR)
>> 
>> -        ldr   r2, =MACH_TYPE_SMDK5250   /* r4 := Arndale machine ID */
>>         /* By default load Arndale defaults values */
>> +        ldr   r2, =MACH_TYPE_SMDK5250       /* r2 := Arndale machine ID */
>>         ldr   r0, =EXYNOS5_TIMER_FREQUENCY  /* r0 := timer's frequency */
>>         ldr   r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */
>> -        /* If it's not the Arndale machine ID, load VE values */
>>         teq   r5, r2
>> +        beq   1f
>> +        /* If it's not the Arndale machine ID, try OMAP5 uEVM */
>> +        ldr   r2, =MACH_TYPE_OMAP5_SEVM     /* r2 := OMAP5 uEVM machine ID */
>> +        ldr   r0, =OMAP5_TIMER_FREQUENCY    /* r0 := timer's frequency */
>> +        ldr   r1, =OMAP5_GIC_BASE_ADDRESS   /* r1 := GIC base address */
>> +        teq   r5, r2
>> +        beq   1f
>> +        /* If it's not the OMAP5432 machine ID, load VE values */
>>         ldrne r0, =V2M_TIMER_FREQUENCY
>>         ldrne r1, =V2M_GIC_BASE_ADDRESS
>> 
>> +1:
>>         /* Ugly: the system timer's frequency register is only
>>          * programmable in Secure state.  Since we don't know where its
>>          * memory-mapped control registers live, we can't find out the
> 
> I'm not in favor to extend this assembly file (see full explanation on
> Ian's mail http://lists.xen.org/archives/html/xen-devel/2013-06/msg01231.html).
> 
> Some ideas to remove this file:
>   - Move kick cpus code later (ie in C code) and per platform
>   - Use U-boot or a bootwrapper to switch CPUs to HYP mode
> 
> Cheers,

Well, it is reasonable.

Actually, I have hacked my u-boot to boot xen in hyp mode. So enter_hyp_mode
is not necessary at least for my situation now.

For "kick cpus codes", I supposed we still need it before we move to the C
code later? In that case, I would like to split this patch to 2 patches (one
with kick cpus code, and one with hyp mode switching). So we could have
a working SMP system on OMAP5 before moving to the new implementation. And
some one who need the hyp mode switching codes could apply the patch, which
won't be applied in mainline, by themselves.

Cheers,

Baozi

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Chen Baozi]

On Aug 15, 2013, at 7:10 PM, Andrii Anisov <andrii.anisov@globallogic.com> wrote:

> 
> The actual mode switch codes is in the end of mode_switch.s：
> 
>         mrs     r0, cpsr        /* Copy the CPSR */
>         add     r0, r0, #0x4    /* 0x16 (Monitor) -> 0x1a (Hyp) */
>         msr     spsr_cxsf, r0   /* into the SPSR */
> 
> Hmmm, I think my patch name should be more accurate. It mainly added
> OMAP5 support in "enter_hyp_mode" routine, which actually makes it
> set cntfrq of arch_timer properly in secure mode.
> 
> Cheers,
> 
> Baozi
> 
> I'm really surprised you have got CPU1 in Secure Supervisor mode.

No, I'm not. I hacked my u-boot to boot in hyp mode directly then.

Baozi


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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Andrii Anisov]

[-- Attachment #1.1: Type: text/plain, Size: 317 bytes --]

Following documentation I have, following code is odd:

+        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base
address */
+        b     kick_cpus_sgi
 kick_cpus_sgi:

CPU1 on being waking by sev checks AUX_CORE_BOOT_0 if it's ok, branches to
AUX_CORE_BOOT_1.
And CPU1 comes to us in supervisor mode.

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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Andrii Anisov]

[-- Attachment #1.1: Type: text/plain, Size: 287 bytes --]

>
> > I'm really surprised you have got CPU1 in Secure Supervisor mode.
>
> No, I'm not. I hacked my u-boot to boot in hyp mode directly then.
>
> Baozi
>
>
But you boot in u-boot CPU0 only.
After kicking CPU1 should come from ROM code in supervisor mode.

*Sincerely,*
*Andrii Anisov.*

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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Chen Baozi]

On Aug 15, 2013, at 7:23 PM, Andrii Anisov <andrii.anisov@globallogic.com> wrote:

> Following documentation I have, following code is odd:
> 
> +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
> +        b     kick_cpus_sgi
>  kick_cpus_sgi:
> 
> CPU1 on being waking by sev checks AUX_CORE_BOOT_0 if it's ok, branches to AUX_CORE_BOOT_1.
> And CPU1 comes to us in supervisor mode.

No, it doesn't. At least, on my board the early_printk log shows:

- CPU 00000001 booting -
- Machine ID 00000ec1 -
- Started in Hyp mode -
- Setting up control registers -
- Turning on paging -
- Ready -

Cheers,

Baozi

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Julien Grall]

On 15 August 2013 12:19, Chen Baozi <baozich@gmail.com> wrote:
>
> On Aug 15, 2013, at 6:03 PM, Julien Grall <julien.grall@linaro.org> wrote:
>
>> On 15 August 2013 10:16, Chen Baozi <baozich@gmail.com> wrote:
>>>
>>> Signed-off-by: Chen Baozi <baozich@gmail.com>
>>> ---
>>> xen/arch/arm/arm32/mode_switch.S      | 34 +++++++++++++++++++++++++++++++---
>>> xen/include/asm-arm/platforms/omap5.h | 17 +++++++++++++++++
>>> 2 files changed, 48 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S
>>> index 3500eb0..e86d3d1 100644
>>> --- a/xen/arch/arm/arm32/mode_switch.S
>>> +++ b/xen/arch/arm/arm32/mode_switch.S
>>> @@ -21,11 +21,13 @@
>>> #include <asm/page.h>
>>> #include <asm/platforms/vexpress.h>
>>> #include <asm/platforms/exynos5.h>
>>> +#include <asm/platforms/omap5.h>
>>> #include <asm/asm_defns.h>
>>> #include <asm/gic.h>
>>>
>>> /* Wake up secondary cpus
>>> - * This code relies on Machine ID and only works for Vexpress and the Arndale
>>> + * This code relies on Machine ID and only works for Vexpress, the Arndale
>>> + * and the OMAP5 uEVM.
>>>  * TODO: Move this code either later (via platform specific desc) or in a bootwrapper
>>>  * r5: Machine ID
>>>  * Clobber r0 r2 */
>>> @@ -34,6 +36,10 @@ kick_cpus:
>>>         ldr   r0, =MACH_TYPE_SMDK5250
>>>         teq   r5, r0                          /* Are we running on the arndale? */
>>>         beq   kick_cpus_arndale
>>> +       /* for OMAP5432 */
>>> +       ldr   r0, =MACH_TYPE_OMAP5_SEVM
>>> +       teq   r5, r0
>>> +       beq   kick_cpus_omap5
>>>         /* otherwise versatile express */
>>>         /* write start paddr to v2m sysreg FLAGSSET register */
>>>         ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO address */
>>> @@ -55,6 +61,20 @@ kick_cpus_arndale:
>>>         str   r2, [r0]
>>>         dsb
>>>         ldr   r2, =EXYNOS5_GIC_BASE_ADDRESS   /* r2 := Exynos5 gic base address */
>>> +       b     kick_cpus_sgi
>>> +kick_cpus_omap5:
>>> +       /* write start paddr to AuxCoreBoot1 where ROM code will jump */
>>> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_1)
>>> +        ldr   r2, =start
>>> +        add   r2, r2, r10
>>> +        str   r2, [r0]
>>> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_0)
>>> +        mov   r2, #0x20
>>> +        str   r2, [r0]
>>> +        dsb
>>> +        sev
>>> +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
>>> +        b     kick_cpus_sgi
>>> kick_cpus_sgi:
>>>         /* send an interrupt */
>>>         ldr   r0, =GIC_DR_OFFSET              /* GIC distributor offset */
>>> @@ -90,15 +110,23 @@ enter_hyp_mode:
>>>         bic   r0, r0, #0xe           /* Clear EA, FIQ and IRQ */
>>>         mcr   CP32(r0, SCR)
>>>
>>> -        ldr   r2, =MACH_TYPE_SMDK5250   /* r4 := Arndale machine ID */
>>>         /* By default load Arndale defaults values */
>>> +        ldr   r2, =MACH_TYPE_SMDK5250       /* r2 := Arndale machine ID */
>>>         ldr   r0, =EXYNOS5_TIMER_FREQUENCY  /* r0 := timer's frequency */
>>>         ldr   r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */
>>> -        /* If it's not the Arndale machine ID, load VE values */
>>>         teq   r5, r2
>>> +        beq   1f
>>> +        /* If it's not the Arndale machine ID, try OMAP5 uEVM */
>>> +        ldr   r2, =MACH_TYPE_OMAP5_SEVM     /* r2 := OMAP5 uEVM machine ID */
>>> +        ldr   r0, =OMAP5_TIMER_FREQUENCY    /* r0 := timer's frequency */
>>> +        ldr   r1, =OMAP5_GIC_BASE_ADDRESS   /* r1 := GIC base address */
>>> +        teq   r5, r2
>>> +        beq   1f
>>> +        /* If it's not the OMAP5432 machine ID, load VE values */
>>>         ldrne r0, =V2M_TIMER_FREQUENCY
>>>         ldrne r1, =V2M_GIC_BASE_ADDRESS
>>>
>>> +1:
>>>         /* Ugly: the system timer's frequency register is only
>>>          * programmable in Secure state.  Since we don't know where its
>>>          * memory-mapped control registers live, we can't find out the
>>
>> I'm not in favor to extend this assembly file (see full explanation on
>> Ian's mail http://lists.xen.org/archives/html/xen-devel/2013-06/msg01231.html).
>>
>> Some ideas to remove this file:
>>   - Move kick cpus code later (ie in C code) and per platform
>>   - Use U-boot or a bootwrapper to switch CPUs to HYP mode
>>
>> Cheers,
>
> Well, it is reasonable.
>
> Actually, I have hacked my u-boot to boot xen in hyp mode. So enter_hyp_mode
> is not necessary at least for my situation now.
>
> For "kick cpus codes", I supposed we still need it before we move to the C
> code later? In that case, I would like to split this patch to 2 patches (one
> with kick cpus code, and one with hyp mode switching). So we could have
> a working SMP system on OMAP5 before moving to the new implementation. And
> some one who need the hyp mode switching codes could apply the patch, which
> won't be applied in mainline, by themselves.

I don't think so. Linux is able to kick cpus in C code, so I don't
find any good reason to keep this code in assembly.
IMHO, the best place is smp_prepare_cpus.

I would prefer to move to the new implementation before adding new
platform SMP support.

Cheers,

-- 
Julien Grall

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Chen Baozi]

On Aug 15, 2013, at 7:40 PM, Julien Grall <julien.grall@linaro.org> wrote:

> On 15 August 2013 12:19, Chen Baozi <baozich@gmail.com> wrote:
>> 
>> On Aug 15, 2013, at 6:03 PM, Julien Grall <julien.grall@linaro.org> wrote:
>> 
>>> On 15 August 2013 10:16, Chen Baozi <baozich@gmail.com> wrote:
>>>> 
>>>> Signed-off-by: Chen Baozi <baozich@gmail.com>
>>>> ---
>>>> xen/arch/arm/arm32/mode_switch.S      | 34 +++++++++++++++++++++++++++++++---
>>>> xen/include/asm-arm/platforms/omap5.h | 17 +++++++++++++++++
>>>> 2 files changed, 48 insertions(+), 3 deletions(-)
>>>> 
>>>> diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S
>>>> index 3500eb0..e86d3d1 100644
>>>> --- a/xen/arch/arm/arm32/mode_switch.S
>>>> +++ b/xen/arch/arm/arm32/mode_switch.S
>>>> @@ -21,11 +21,13 @@
>>>> #include <asm/page.h>
>>>> #include <asm/platforms/vexpress.h>
>>>> #include <asm/platforms/exynos5.h>
>>>> +#include <asm/platforms/omap5.h>
>>>> #include <asm/asm_defns.h>
>>>> #include <asm/gic.h>
>>>> 
>>>> /* Wake up secondary cpus
>>>> - * This code relies on Machine ID and only works for Vexpress and the Arndale
>>>> + * This code relies on Machine ID and only works for Vexpress, the Arndale
>>>> + * and the OMAP5 uEVM.
>>>> * TODO: Move this code either later (via platform specific desc) or in a bootwrapper
>>>> * r5: Machine ID
>>>> * Clobber r0 r2 */
>>>> @@ -34,6 +36,10 @@ kick_cpus:
>>>>        ldr   r0, =MACH_TYPE_SMDK5250
>>>>        teq   r5, r0                          /* Are we running on the arndale? */
>>>>        beq   kick_cpus_arndale
>>>> +       /* for OMAP5432 */
>>>> +       ldr   r0, =MACH_TYPE_OMAP5_SEVM
>>>> +       teq   r5, r0
>>>> +       beq   kick_cpus_omap5
>>>>        /* otherwise versatile express */
>>>>        /* write start paddr to v2m sysreg FLAGSSET register */
>>>>        ldr   r0, =(V2M_SYS_MMIO_BASE)        /* base V2M sysreg MMIO address */
>>>> @@ -55,6 +61,20 @@ kick_cpus_arndale:
>>>>        str   r2, [r0]
>>>>        dsb
>>>>        ldr   r2, =EXYNOS5_GIC_BASE_ADDRESS   /* r2 := Exynos5 gic base address */
>>>> +       b     kick_cpus_sgi
>>>> +kick_cpus_omap5:
>>>> +       /* write start paddr to AuxCoreBoot1 where ROM code will jump */
>>>> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_1)
>>>> +        ldr   r2, =start
>>>> +        add   r2, r2, r10
>>>> +        str   r2, [r0]
>>>> +        ldr   r0, =(OMAP_AUX_CORE_BOOT_0)
>>>> +        mov   r2, #0x20
>>>> +        str   r2, [r0]
>>>> +        dsb
>>>> +        sev
>>>> +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base address */
>>>> +        b     kick_cpus_sgi
>>>> kick_cpus_sgi:
>>>>        /* send an interrupt */
>>>>        ldr   r0, =GIC_DR_OFFSET              /* GIC distributor offset */
>>>> @@ -90,15 +110,23 @@ enter_hyp_mode:
>>>>        bic   r0, r0, #0xe           /* Clear EA, FIQ and IRQ */
>>>>        mcr   CP32(r0, SCR)
>>>> 
>>>> -        ldr   r2, =MACH_TYPE_SMDK5250   /* r4 := Arndale machine ID */
>>>>        /* By default load Arndale defaults values */
>>>> +        ldr   r2, =MACH_TYPE_SMDK5250       /* r2 := Arndale machine ID */
>>>>        ldr   r0, =EXYNOS5_TIMER_FREQUENCY  /* r0 := timer's frequency */
>>>>        ldr   r1, =EXYNOS5_GIC_BASE_ADDRESS /* r1 := GIC base address */
>>>> -        /* If it's not the Arndale machine ID, load VE values */
>>>>        teq   r5, r2
>>>> +        beq   1f
>>>> +        /* If it's not the Arndale machine ID, try OMAP5 uEVM */
>>>> +        ldr   r2, =MACH_TYPE_OMAP5_SEVM     /* r2 := OMAP5 uEVM machine ID */
>>>> +        ldr   r0, =OMAP5_TIMER_FREQUENCY    /* r0 := timer's frequency */
>>>> +        ldr   r1, =OMAP5_GIC_BASE_ADDRESS   /* r1 := GIC base address */
>>>> +        teq   r5, r2
>>>> +        beq   1f
>>>> +        /* If it's not the OMAP5432 machine ID, load VE values */
>>>>        ldrne r0, =V2M_TIMER_FREQUENCY
>>>>        ldrne r1, =V2M_GIC_BASE_ADDRESS
>>>> 
>>>> +1:
>>>>        /* Ugly: the system timer's frequency register is only
>>>>         * programmable in Secure state.  Since we don't know where its
>>>>         * memory-mapped control registers live, we can't find out the
>>> 
>>> I'm not in favor to extend this assembly file (see full explanation on
>>> Ian's mail http://lists.xen.org/archives/html/xen-devel/2013-06/msg01231.html).
>>> 
>>> Some ideas to remove this file:
>>>  - Move kick cpus code later (ie in C code) and per platform
>>>  - Use U-boot or a bootwrapper to switch CPUs to HYP mode
>>> 
>>> Cheers,
>> 
>> Well, it is reasonable.
>> 
>> Actually, I have hacked my u-boot to boot xen in hyp mode. So enter_hyp_mode
>> is not necessary at least for my situation now.
>> 
>> For "kick cpus codes", I supposed we still need it before we move to the C
>> code later? In that case, I would like to split this patch to 2 patches (one
>> with kick cpus code, and one with hyp mode switching). So we could have
>> a working SMP system on OMAP5 before moving to the new implementation. And
>> some one who need the hyp mode switching codes could apply the patch, which
>> won't be applied in mainline, by themselves.
> 
> I don't think so. Linux is able to kick cpus in C code, so I don't
> find any good reason to keep this code in assembly.
> IMHO, the best place is smp_prepare_cpus.
> 
> I would prefer to move to the new implementation before adding new
> platform SMP support.

Ok. So any plans of the new implementation? I mean, if it is still not
on schedule, I may have a try...

Cheers,

Baozi

Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Andrii Anisov]

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Well, I have looked through the u-boot, and have one more question, do you
have HS chip on your board?

Sincerely,
Andrii Anisov.


On Thu, Aug 15, 2013 at 2:45 PM, Chen Baozi <baozich@gmail.com> wrote:

> I use the u-boot_2013.01.1.1 shipped with TI and patched commit c4a4e2e
> of the mainline u-boot.
>
> And I think the latest upstream u-boot should work too, since it already
> has that commit. And a netbsd guy told me the upstream u-boot works for
> him.
>
> Cheers,
>
> Baozi
>
> On Aug 15, 2013, at 7:38 PM, Andrii Anisov <andrii.anisov@globallogic.com>
> wrote:
>
> >
> > On Thu, Aug 15, 2013 at 2:28 PM, Chen Baozi <baozich@gmail.com> wrote:
> >
> > On Aug 15, 2013, at 7:23 PM, Andrii Anisov <
> andrii.anisov@globallogic.com> wrote:
> >
> > > Following documentation I have, following code is odd:
> > >
> > > +        ldr   r2, =OMAP5_GIC_BASE_ADDRESS     /* r2 := OMAP5 gic base
> address */
> > > +        b     kick_cpus_sgi
> > >  kick_cpus_sgi:
> > >
> > > CPU1 on being waking by sev checks AUX_CORE_BOOT_0 if it's ok,
> branches to AUX_CORE_BOOT_1.
> > > And CPU1 comes to us in supervisor mode.
> >
> > No, it doesn't. At least, on my board the early_printk log shows:
> >
> > - CPU 00000001 booting -
> > - Machine ID 00000ec1 -
> > - Started in Hyp mode -
> > - Setting up control registers -
> > - Turning on paging -
> > - Ready -
> >
> > Cheers,
> >
> > Baozi
> >
> > Wow!
> >
> > Could you please share you hacks to u-boot to analyze?
> > I do use omapboot. Rely on this http://review.omapzoom.org/#/c/31816/switching to HYP using ROM code API. And I have my secondary CPU come to me
> in supervisor mode.
> >
> > I hope it's not and offtopic for the list.
> >
> > Sincerely,
> > Andrii Anisov.
> >
>
>

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Re: [PATCH] xen/arm: Support kick cpus and switch to hypervisor for the OMAP5

[Ian Campbell]

On Thu, 2013-08-15 at 11:03 +0100, Julien Grall wrote:
> I'm not in favor to extend this assembly file (see full explanation on
> Ian's mail http://lists.xen.org/archives/html/xen-devel/2013-06/msg01231.html).
> 
> Some ideas to remove this file:
>    - Move kick cpus code later (ie in C code) and per platform
>    - Use U-boot or a bootwrapper to switch CPUs to HYP mode

Strangely enough I was just working on this bootwrapper stuff earlier in
the week (I just sent another mail about it). It's not there for the
kick cpu stuff yet but I have some ideas...

I expect we will actually want to do both of the things you suggest. If
the firmware does not leave secondary CPUs in a state where they can be
kicked from NS HYP mode or cause them to start in NS HYP then we will
need boot-wrapper to paper over this and make it look that way to Xen.

Then the kick cpus code in Xen can be moved later, hopefully as late as
the existing cpu_up code, although this might need some rejigging of how
we do the pagetable bootstrapping.

Ian.