From mboxrd@z Thu Jan 1 00:00:00 1970 From: Konrad Rzeszutek Wilk Subject: Re: Multi-bridged PCIe devices (Was: Re: iommuu/vt-d issues with LSI MegaSAS (PERC5i)) Date: Tue, 7 Jan 2014 10:40:16 -0500 Message-ID: <20140107154016.GA7680@phenom.dumpdata.com> References: <6748185fb950f1aca45678675dc87b0f@mail.shatteredsilicon.net> <52CBFDDD020000780011112C@nat28.tlf.novell.com> <5dcec6d652a27688050262f949e9dc9e@mail.shatteredsilicon.net> <20140107143836.GF3588@phenom.dumpdata.com> <52CC218B0200007800111330@nat28.tlf.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <52CC218B0200007800111330@nat28.tlf.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Andrew Cooper , Gordan Bobic , Feng Wu , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On Tue, Jan 07, 2014 at 02:47:23PM +0000, Jan Beulich wrote: > >>> On 07.01.14 at 15:38, Konrad Rzeszutek Wilk wrote: > > That requires knowing the MMIO BARs the 'fake' device has, and > > .. well, whatever else the Intel VT-d code requires. > > Why would you need to know BAR values? Weren't we talking of > an invisible bridge (in which case one would expect that there's > no MSI-X interrupts to be used, which is the only reason I can > see us needing to know/read the BARs)? I mispoke. I was thinking about the 'memory behind the bridge' is what I need to add in somehwere. I really need to look at the VT-d spec and implementation to see what data I need to provide to it. > > Jan >