From mboxrd@z Thu Jan  1 00:00:00 1970
From: Peng Fan <b51431@freescale.com>
Subject: Re: [PATCH 1/2] xen: arm: traps: check hsr.ec for ARM32
Date: Mon, 21 Sep 2015 16:41:42 +0800
Message-ID: <20150921084138.GA31297@shlinux2>
References: <1442819224-25390-1-git-send-email-Peng.Fan@freescale.com>
	<55FFD22B.4090601@citrix.com>
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To: Julien Grall <julien.grall@citrix.com>
Cc: Peng Fan <Peng.Fan@freescale.com>, Stefano Stabellini <stefano.stabellini@citrix.com>, Ian Campbell <ian.campbell@citrix.com>, xen-devel@lists.xen.org
List-Id: xen-devel@lists.xenproject.org

Hi Julien,
On Mon, Sep 21, 2015 at 10:47:23AM +0100, Julien Grall wrote:
>Hi Peng,
>
>On 21/09/15 08:07, Peng Fan wrote:
>> To ARM64, "if ( hsr.ec >= 0x10 ) return 1;" is ok for unconditional
>> check, but to ARM32, we need to use 'hsr.ec >> 30' to check.
>
>hsr.ec is encoded on 5 bits, therefore the shift you suggest is wrong.
>Maybe you wanted to use (hsr.ec >> 4)?
Thanks for correcting me. 0x10 can handle hsr.ec >> 4.
My bad, this patch is wrong. 

Regards,
Peng.
>
>Although, can you explain why you need a different check for ARM32?
>
>Regards,
>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>> Cc: Ian Campbell <ian.campbell@citrix.com>
>> Cc: Stefano Stabellini <stefano.stabellini@citrix.com>
>> Cc: Julien Grall <julien.grall@citrix.com>
>> ---
>>  xen/arch/arm/traps.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
>> index 9d2bd6a..2e2b1f2 100644
>> --- a/xen/arch/arm/traps.c
>> +++ b/xen/arch/arm/traps.c
>> @@ -1531,8 +1531,13 @@ static int check_conditional_instr(struct cpu_user_regs *regs,
>>      int cond;
>>  
>>      /* Unconditional Exception classes */
>> +#ifdef CONFIG_ARM_64
>>      if ( hsr.ec >= 0x10 )
>>          return 1;
>> +#else
>> +    if ( hsr.ec >> 30 )
>> +        return 1;
>> +#endif
>>  
>>      /* Check for valid condition in hsr */
>>      cond = hsr.cond.ccvalid ? hsr.cond.cc : -1;
>> 
>
>
>-- 
>Julien Grall

--