From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Zhang, Haozhong" Subject: Re: [PATCH v2 2/2] x86/hvm: add support for pcommit instruction Date: Tue, 5 Jan 2016 15:15:00 +0800 Message-ID: <20160105071500.GA2440@hz-desktop.sh.intel.com> References: <1451476139-22148-1-git-send-email-haozhong.zhang@intel.com> <1451476139-22148-3-git-send-email-haozhong.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Tian, Kevin" Cc: Wei Liu , Ian Campbell , Stefano Stabellini , "Nakajima, Jun" , Andrew Cooper , Ian Jackson , "xen-devel@lists.xen.org" , Jan Beulich , Keir Fraser List-Id: xen-devel@lists.xenproject.org On 01/05/16 15:08, Tian, Kevin wrote: > > From: Zhang, Haozhong > > Sent: Wednesday, December 30, 2015 7:49 PM > > > > Pass PCOMMIT CPU feature into HMV domain. Currently, we do not intercept > > pcommit instruction for L1 guest, and allow L1 to intercept pcommit > > instruction for L2 guest. > > Could you elaborate why different policies are used for L1/L2? And better > add a comment in code (at least for vvmx) to describe the intention. > > Thanks > Kevin The intention is that we completely expose pcommit (both the instruction and VMEXIT caused by pcommit) to L1. Haozhong