* [PATCH] x86: MISALIGNSSE feature depends on SSE
@ 2016-10-24 12:17 Jan Beulich
2016-10-24 14:10 ` Andrew Cooper
0 siblings, 1 reply; 3+ messages in thread
From: Jan Beulich @ 2016-10-24 12:17 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Wei Liu
[-- Attachment #1: Type: text/plain, Size: 767 bytes --]
Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -196,8 +196,9 @@ def crunch_numbers(state):
# SSE is taken to mean support for the %XMM registers as well as the
# instructions. Several futher instruction sets are built on core
- # %XMM support, without specific inter-dependencies.
- SSE: [SSE2, SSE3, SSSE3, SSE4A,
+ # %XMM support, without specific inter-dependencies. Additionally
+ # AMD has a special mis-alignment sub-mode.
+ SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
AESNI, SHA],
# SSE2 was re-specified as core instructions for 64bit.
[-- Attachment #2: x86-misalignsse-dep.patch --]
[-- Type: text/plain, Size: 806 bytes --]
x86: MISALIGNSSE feature depends on SSE
Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -196,8 +196,9 @@ def crunch_numbers(state):
# SSE is taken to mean support for the %XMM registers as well as the
# instructions. Several futher instruction sets are built on core
- # %XMM support, without specific inter-dependencies.
- SSE: [SSE2, SSE3, SSSE3, SSE4A,
+ # %XMM support, without specific inter-dependencies. Additionally
+ # AMD has a special mis-alignment sub-mode.
+ SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
AESNI, SHA],
# SSE2 was re-specified as core instructions for 64bit.
[-- Attachment #3: Type: text/plain, Size: 127 bytes --]
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] x86: MISALIGNSSE feature depends on SSE
2016-10-24 12:17 [PATCH] x86: MISALIGNSSE feature depends on SSE Jan Beulich
@ 2016-10-24 14:10 ` Andrew Cooper
2016-10-24 14:21 ` Wei Liu
0 siblings, 1 reply; 3+ messages in thread
From: Andrew Cooper @ 2016-10-24 14:10 UTC (permalink / raw)
To: Jan Beulich, xen-devel; +Cc: Wei Liu
On 24/10/16 13:17, Jan Beulich wrote:
> Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -196,8 +196,9 @@ def crunch_numbers(state):
>
> # SSE is taken to mean support for the %XMM registers as well as the
> # instructions. Several futher instruction sets are built on core
> - # %XMM support, without specific inter-dependencies.
> - SSE: [SSE2, SSE3, SSSE3, SSE4A,
> + # %XMM support, without specific inter-dependencies. Additionally
> + # AMD has a special mis-alignment sub-mode.
> + SSE: [SSE2, SSE3, SSSE3, SSE4A, MISALIGNSSE,
> AESNI, SHA],
>
> # SSE2 was re-specified as core instructions for 64bit.
>
>
>
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: MISALIGNSSE feature depends on SSE
2016-10-24 14:10 ` Andrew Cooper
@ 2016-10-24 14:21 ` Wei Liu
0 siblings, 0 replies; 3+ messages in thread
From: Wei Liu @ 2016-10-24 14:21 UTC (permalink / raw)
To: Andrew Cooper; +Cc: xen-devel, Wei Liu, Jan Beulich
On Mon, Oct 24, 2016 at 03:10:49PM +0100, Andrew Cooper wrote:
> On 24/10/16 13:17, Jan Beulich wrote:
> > Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
> > Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
>
Release-acked-by: Wei Liu <wei.liu2@citrix.com>
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-10-24 12:17 [PATCH] x86: MISALIGNSSE feature depends on SSE Jan Beulich
2016-10-24 14:10 ` Andrew Cooper
2016-10-24 14:21 ` Wei Liu
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