From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: Yi Sun <yi.y.sun@linux.intel.com>
Cc: wei.liu2@citrix.com, he.chen@linux.intel.com,
andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
ian.jackson@eu.citrix.com, mengxu@cis.upenn.edu,
jbeulich@suse.com, chao.p.peng@linux.intel.com,
xen-devel@lists.xenproject.org
Subject: Re: [PATCH RESEND v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document
Date: Mon, 30 Jan 2017 15:39:28 -0500 [thread overview]
Message-ID: <20170130203928.GA10525@char.us.oracle.com> (raw)
In-Reply-To: <20170130181033.GA10662@char.us.ORACLE.com>
> > +# Testing
> > +
> > +L2 CAT uses same xl interfaces as L3 CAT/CDP. So, we can execute these
> > +commands to verify L2 CAT and L3 CAT/CDP on different HWs support them.
> > +
> > +For example:
> > + root@:~$ xl psr-hwinfo --cat
> > + Cache Allocation Technology (CAT): L2
> > + Socket ID : 0
> > + Maximum COS : 3
> > + CBM length : 8
> > + Default CBM : 0xff
> > +
> > + root@:~$ xl psr-cat-cbm-set -l2 1 0x7f
> > +
> > + root@:~$ xl psr-cat-show -l2 1
> > + Socket ID : 0
> > + Default CBM : 0xff
> > + ID NAME CBM
> > + 1 ubuntu14 0x7f
> > +
I tried finding the Intel SDM (December 2016) what the format
of CBM is as the value '0x7f' does not really mean much to me.
Right above Figure 17.28 it says:
"Figure 17-27 also shows three examples of sets of Cache Capacity Bitmasks. For simplicity these are represented
as 8-bit vectors, though this may vary _depending on the implementation and how the mask is mapped to the avail-
able cache capacity._"
So in other words - not documented.
Then later is says:
" Rather, this is a convenient manner to represent capacity,
overlap and isolation of cache space. For example, executing a POPCNT instruction (population count of set bits) on
the capacity bitmask can provide the fraction of cache space that a class of service can allocate into."
OK, so _can_ (but not _MUST_), so again implementation specific - and
can provide a fraction of cache space.
Which would imply that the values could be:
0x0F - half of L2
0x03 - quarter of L2
Is there some other documentation that explains this in more details?
If it is like I mentioned would it make sense to have 'xl' be capable
of dealing with string values? such as "three-quarters", "half", etc
and then set it? Or percentage and map that to the correct value?
Like:
xl psr-cat-cbm-set -l2 ubuntu14 50%
would be quite obvious instead of say 0x0F?
Thanks.
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next prev parent reply other threads:[~2017-01-30 20:39 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-19 6:01 [PATCH RESEND v5 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 01/24] docs: create L2 Cache Allocation Technology (CAT) feature document Yi Sun
2017-01-20 9:39 ` Tian, Kevin
2017-01-22 2:15 ` Yi Sun
2017-02-08 6:45 ` Tian, Kevin
2017-01-30 18:10 ` Konrad Rzeszutek Wilk
2017-01-30 20:39 ` Konrad Rzeszutek Wilk [this message]
2017-02-04 7:24 ` Yi Sun
2017-02-04 7:06 ` Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 02/24] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-01-30 22:05 ` Konrad Rzeszutek Wilk
2017-01-19 6:01 ` [PATCH RESEND v5 03/24] x86: refactor psr: implement main data structures Yi Sun
2017-01-30 22:20 ` Konrad Rzeszutek Wilk
2017-01-31 10:10 ` Jan Beulich
2017-01-31 14:12 ` Konrad Rzeszutek Wilk
2017-01-31 15:07 ` Jan Beulich
2017-01-31 17:32 ` Konrad Rzeszutek Wilk
2017-02-05 1:53 ` Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 04/24] x86: refactor psr: implement CPU init and free flow Yi Sun
2017-01-31 2:44 ` Konrad Rzeszutek Wilk
2017-01-31 10:14 ` Jan Beulich
2017-01-31 14:13 ` Konrad Rzeszutek Wilk
2017-01-31 10:53 ` Andrew Cooper
2017-01-19 6:01 ` [PATCH RESEND v5 05/24] x86: refactor psr: implement Domain init/free and schedule flows Yi Sun
2017-01-31 19:52 ` Konrad Rzeszutek Wilk
2017-01-19 6:01 ` [PATCH RESEND v5 06/24] x86: refactor psr: implement get hw info flow Yi Sun
2017-01-31 20:17 ` Konrad Rzeszutek Wilk
2017-01-19 6:01 ` [PATCH RESEND v5 07/24] x86: refactor psr: implement get value flow Yi Sun
2017-01-31 20:29 ` Konrad Rzeszutek Wilk
2017-02-07 2:47 ` Yi Sun
2017-02-07 13:56 ` Konrad Rzeszutek Wilk
2017-01-19 6:01 ` [PATCH RESEND v5 08/24] x86: refactor psr: set value: implement framework Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 09/24] x86: refactor psr: set value: assemble features value array Yi Sun
2017-01-31 20:57 ` Konrad Rzeszutek Wilk
2017-02-07 2:51 ` Yi Sun
2017-02-07 13:57 ` Konrad Rzeszutek Wilk
2017-01-19 6:01 ` [PATCH RESEND v5 10/24] x86: refactor psr: set value: implement cos finding flow Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 11/24] x86: refactor psr: set value: implement cos id picking flow Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 12/24] x86: refactor psr: set value: implement write msr flow Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 13/24] x86: refactor psr: implement CPU init and free flow for CDP Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 14/24] x86: refactor psr: implement get hw info " Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 15/24] x86: refactor psr: implement get value " Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 16/24] x86: refactor psr: implement set value callback functions " Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 17/24] x86: L2 CAT: implement CPU init and free flow Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 18/24] x86: L2 CAT: implement get hw info flow Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 19/24] x86: L2 CAT: implement get value flow Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 20/24] x86: L2 CAT: implement set " Yi Sun
2017-01-19 6:01 ` [PATCH RESEND v5 21/24] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-01-27 15:18 ` Wei Liu
2017-01-19 6:01 ` [PATCH RESEND v5 22/24] tools: L2 CAT: support show cbm " Yi Sun
2017-01-27 15:18 ` Wei Liu
2017-01-19 6:01 ` [PATCH RESEND v5 23/24] tools: L2 CAT: support set " Yi Sun
2017-01-27 15:18 ` Wei Liu
2017-01-19 6:01 ` [PATCH RESEND v5 24/24] docs: add L2 CAT description in docs Yi Sun
2017-01-27 15:18 ` Wei Liu
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