From mboxrd@z Thu Jan 1 00:00:00 1970 From: Haozhong Zhang Subject: [PATCH 05/19] x86/mce: merge loops to get Intel extended MC MSR Date: Fri, 17 Feb 2017 14:39:22 +0800 Message-ID: <20170217063936.13208-6-haozhong.zhang@intel.com> References: <20170217063936.13208-1-haozhong.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170217063936.13208-1-haozhong.zhang@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel@lists.xen.org Cc: Haozhong Zhang , Christoph Egger , Andrew Cooper , Jan Beulich , Liu Jinsong List-Id: xen-devel@lists.xenproject.org VGhlIHNlY29uZCBsb29wIHRoYXQgZ2V0cyBNU1JfSUEzMl9NQ0dfUjggdG8gTVNSX0lBMzJfTUNH X1IxNSB3YXMKc3Vycm91bmRlZCBieSAnI2lmZGVmIF9fWDg2XzY0X18gLi4uICNlbmRpZicgYW5k IGhhZCB0byBiZSBzZXBlcmF0ZWQKZnJvbSB0aGUgZmlyc3QgbG9vcCB0aGF0IGdldHMgTVNSX0lB MzJfTUNHX0VBWCB0byBNU1JfSUEzMl9NQ0dfTUlTQy4KQmVjYXVzZSBYZW4gaGFkIGRyb3BwZWQg c3VwcG9ydCBmb3IgMzItYml0IHg4NiBob3N0LCB0aGVzZSB0d28gbG9vcHMKY2FuIGJlIG1lcmdl ZCBub3cuCgpTaWduZWQtb2ZmLWJ5OiBIYW96aG9uZyBaaGFuZyA8aGFvemhvbmcuemhhbmdAaW50 ZWwuY29tPgotLS0KQ2M6IENocmlzdG9waCBFZ2dlciA8Y2hlZ2dlckBhbWF6b24uZGU+CkNjOiBM aXUgSmluc29uZyA8amluc29uZy5saXVAYWxpYmFiYS1pbmMuY29tPgpDYzogSmFuIEJldWxpY2gg PGpiZXVsaWNoQHN1c2UuY29tPgpDYzogQW5kcmV3IENvb3BlciA8YW5kcmV3LmNvb3BlcjNAY2l0 cml4LmNvbT4KLS0tCiB4ZW4vYXJjaC94ODYvY3B1L21jaGVjay9tY2VfaW50ZWwuYyB8IDUgKy0t LS0KIDEgZmlsZSBjaGFuZ2VkLCAxIGluc2VydGlvbigrKSwgNCBkZWxldGlvbnMoLSkKCmRpZmYg LS1naXQgYS94ZW4vYXJjaC94ODYvY3B1L21jaGVjay9tY2VfaW50ZWwuYyBiL3hlbi9hcmNoL3g4 Ni9jcHUvbWNoZWNrL21jZV9pbnRlbC5jCmluZGV4IDAwNWU0MWQuLjQ5OGU4ZTQgMTAwNjQ0Ci0t LSBhL3hlbi9hcmNoL3g4Ni9jcHUvbWNoZWNrL21jZV9pbnRlbC5jCisrKyBiL3hlbi9hcmNoL3g4 Ni9jcHUvbWNoZWNrL21jZV9pbnRlbC5jCkBAIC0yMTEsMTAgKzIxMSw3IEBAIGludGVsX2dldF9l eHRlbmRlZF9tc3JzKHN0cnVjdCBtY2luZm9fZ2xvYmFsICptaWcsIHN0cnVjdCBtY19pbmZvICpt aSkKICAgICBtY19leHQtPmNvbW1vbi50eXBlID0gTUNfVFlQRV9FWFRFTkRFRDsKICAgICBtY19l eHQtPmNvbW1vbi5zaXplID0gc2l6ZW9mKHN0cnVjdCBtY2luZm9fZXh0ZW5kZWQpOwogCi0gICAg Zm9yIChpID0gTVNSX0lBMzJfTUNHX0VBWDsgaSA8PSBNU1JfSUEzMl9NQ0dfTUlTQzsgaSsrKQot ICAgICAgICBpbnRlbF9nZXRfZXh0ZW5kZWRfbXNyKG1jX2V4dCwgaSk7Ci0KLSAgICBmb3IgKGkg PSBNU1JfSUEzMl9NQ0dfUjg7IGkgPD0gTVNSX0lBMzJfTUNHX1IxNTsgaSsrKQorICAgIGZvciAo aSA9IE1TUl9JQTMyX01DR19FQVg7IGkgPD0gTVNSX0lBMzJfTUNHX1IxNTsgaSsrKQogICAgICAg ICBpbnRlbF9nZXRfZXh0ZW5kZWRfbXNyKG1jX2V4dCwgaSk7CiAKICAgICByZXR1cm4gbWNfZXh0 OwotLSAKMi4xMC4xCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX18KWGVuLWRldmVsIG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRw czovL2xpc3RzLnhlbi5vcmcveGVuLWRldmVsCg==