[PATCH 0/5] x86/dpci: bind legacy PCI interrupts to PVHv2 Dom0

[Roger Pau Monne <roger.pau@citrix.com>]

Hello,

The following patches allow binding bare-metal GSIs into a PVHv2 Dom0, by
snooping on the vIO APICs writes made by Dom0.

In order to implement this a new PT_IRQ_TYPE_GSI bind type has to be
introduced, since PT_IRQ_TYPE_PCI is not suitable because Xen doesn't know the
PCI device(s) behind each GSI. Most of the code is shared with the
PT_IRQ_TYPE_PCI bind type, except for the EOI. The actual binding of the GSI
into Dom0 is performed when Dom0 unmasks the vIO APIC pin.

Patches #3 and #5 is where the actual meat is. The rest are mostly prerequisite
changes for those two.

The series has been tested with a PVHv2 Dom0 on a box with 3 IO APICs,
although all devices are wired up into the first IO APIC sadly.

A branch with the changes can be found at:

git://xenbits.xen.org/people/royger/xen.git dom0_gsi_v1

Note that this builds on top of the "x86/vioapic: introduce support for
multiple vIO APICs" series.

Thanks, Roger.


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