From: Chao Gao <chao.gao@intel.com>
To: Roger Pau Monne <roger.pau@citrix.com>
Cc: xen-devel@lists.xenproject.org,
Julien Grall <julien.grall@arm.com>,
Jan Beulich <jbeulich@suse.com>,
Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH for-4.9] x86/vioapic: allow holes in the GSI range for PVH Dom0
Date: Tue, 18 Apr 2017 02:20:07 +0800 [thread overview]
Message-ID: <20170417182007.GA5914@skl-2s3.sh.intel.com> (raw)
In-Reply-To: <20170417160922.76016-1-roger.pau@citrix.com>
On Mon, Apr 17, 2017 at 05:09:22PM +0100, Roger Pau Monne wrote:
>The current vIO APIC for PVH Dom0 doesn't allow non-contiguous GSIs, which
>means that all GSIs must belong to an IO APIC. This doesn't match reality,
>where there are systems with non-contiguous GSIs.
>
>In order to fix this add a base_gsi field to each hvm_vioapic struct, in order
>to store the base GSI for each emulated IO APIC. For PVH Dom0 those values are
>populated based on the hardware ones.
>
>Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
>Reported-by: Chao Gao <chao.gao@intel.com>
Tested-by: Chao Gao <chao.gao@intel.com>
Thanks
Chao
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next prev parent reply other threads:[~2017-04-18 1:23 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-17 16:09 [PATCH for-4.9] x86/vioapic: allow holes in the GSI range for PVH Dom0 Roger Pau Monne
2017-04-17 18:20 ` Chao Gao [this message]
2017-04-18 7:02 ` Roger Pau Monne
2017-04-18 8:39 ` Jan Beulich
2017-04-18 8:49 ` Roger Pau Monne
2017-04-18 8:51 ` Andrew Cooper
2017-04-18 9:00 ` Jan Beulich
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