[PATCH] Fix hypervisor crash when writing to VPMU MSR

[Mohit Gambhir <mohit.gambhir@oracle.com>]

In order to address the concerns raised in XSA-163, I am writing XTF based
tests to validate PMU MSR read/writes from HVM guests. 

While testing, I found a scenario where setting the Pin Control Flag bit (19) 
of IA32_PERF_EVTSELx results in a General Protection Fault followed by a
hypervisor crash. While Intel SDM Vol 3B, Section 18.2.1.1 Architectural 
Performance Monitoring Version 1 Facilities, describes the bit functionality, 
it is unclear why the fault happens. 

There are two possible solutions to prevent the hypervisor from crashing:

1. Mask the PC bit in the VPMU so as to not allow any writes to it from guests
on any Intel machine. 

2. Use wrmsr_safe() function to write to IA32_PERF_EVTSELx register and return
any resulting fault to the guest OS.

The attached patch uses solution 2 so as to not disable PC flag bit on machines
that do not fault. 

Mohit Gambhir (1):
  x86/vpmu_intel: Fix hypervisor crash by catching wrmsr fault

 xen/arch/x86/cpu/vpmu_intel.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

-- 
2.9.3


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