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From: Mohit Gambhir <mohit.gambhir@oracle.com>
To: andrew.cooper3@citrix.com, xen-devel@lists.xen.org
Cc: boris.ostrovsky@oracle.com, Mohit Gambhir <mohit.gambhir@oracle.com>
Subject: [PATCH v2 1/2][XTF] xtf/vpmu: Add Intel PMU MSR addresses
Date: Mon, 24 Apr 2017 13:46:07 -0400	[thread overview]
Message-ID: <20170424174608.32026-2-mohit.gambhir@oracle.com> (raw)
In-Reply-To: <20170424174608.32026-1-mohit.gambhir@oracle.com>

This patch adds Intel PMU MSR addresses as macros for VPMU testing

Signed-off-by: Mohit Gambhir <mohit.gambhir@oracle.com>
---
 arch/x86/include/arch/msr-index.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h
index 2e90079..3a79025 100644
--- a/arch/x86/include/arch/msr-index.h
+++ b/arch/x86/include/arch/msr-index.h
@@ -38,6 +38,17 @@
 #define MSR_GS_BASE                     0xc0000101
 #define MSR_SHADOW_GS_BASE              0xc0000102
 
+#define MSR_IA32_PMC(n)                 (0x000000c1 + (n))
+#define MSR_IA32_PERFEVTSEL(n)          (0x00000186 + (n))
+#define MSR_IA32_DEBUGCTL                0x000001d9
+#define MSR_IA32_FIXED_CTR(n)           (0x00000309 + (n))
+#define MSR_IA32_FIXED_CTR_CTRL          0x0000038d
+#define MSR_IA32_PERF_GLOBAL_CTRL        0x0000038f
+#define MSR_IA32_PERF_GLOBAL_STATUS      0x0000038e
+#define MSR_IA32_PERF_GLOBAL_OVF_CTRL    0x00000390
+#define MSR_IA32_PERF_CAPABILITIES       0x00000345
+#define MSR_IA32_A_PMC(n)               (0x000004c1 + (n))
+
 #endif /* XFT_X86_MSR_INDEX_H */
 
 /*
-- 
2.9.3


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  reply	other threads:[~2017-04-24 17:46 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-24 17:46 [PATCH v2 0/2][XTF] xtf/vpmu VPMU tests Mohit Gambhir
2017-04-24 17:46 ` Mohit Gambhir [this message]
2017-04-24 17:49   ` [PATCH v2 1/2][XTF] xtf/vpmu: Add Intel PMU MSR addresses Mohit Gambhir
2017-04-24 17:46 ` [PATCH v2 2/2][XTF] xtf/vpmu: MSR read/write tests for VPMU Mohit Gambhir

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