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From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	he.chen@linux.intel.com, andrew.cooper3@citrix.com,
	dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
	mengxu@cis.upenn.edu, xen-devel@lists.xenproject.org,
	chao.p.peng@linux.intel.com, roger.pau@citrix.com
Subject: Re: [PATCH v11 08/23] x86: refactor psr: L3 CAT: set value: implement framework.
Date: Tue, 6 Jun 2017 16:18:51 +0800	[thread overview]
Message-ID: <20170606081851.GR3420@yi.y.sun> (raw)
In-Reply-To: <59367924020000780015F9EC@prv-mh.provo.novell.com>

On 17-06-06 01:43:00, Jan Beulich wrote:
> >>> On 02.06.17 at 04:49, <yi.y.sun@linux.intel.com> wrote:
> > On 17-06-01 04:45:58, Jan Beulich wrote:
> >> >>> On 01.06.17 at 12:00, <yi.y.sun@linux.intel.com> wrote:
> >> > On 17-05-30 08:32:59, Jan Beulich wrote:
> >> >> >>> On 03.05.17 at 10:44, <yi.y.sun@linux.intel.com> wrote:
> >> >> > --- a/xen/arch/x86/psr.c
> >> >> > +++ b/xen/arch/x86/psr.c
> >> >> > @@ -118,11 +118,13 @@ static const struct feat_props {
> >> >> >   *             COS ID. Every entry of cos_ref corresponds to one COS ID.
> >> >> >   */
> >> >> >  struct psr_socket_info {
> >> >> > -    bool feat_init;
> >> >> > -    spinlock_t ref_lock;
> >> >> >      /* Feature array's index is 'enum psr_feat_type' which is same as 'props' */
> >> >> >      struct feat_node *features[PSR_SOCKET_FEAT_NUM];
> >> >> > +    bool feat_init;
> >> >> >      unsigned int cos_ref[MAX_COS_REG_CNT];
> >> >> > +    spinlock_t ref_lock;
> >> >> 
> >> >> This shuffling of fields seems unmotivated and is not being explained
> >> >> in the description.
> >> >> 
> >> > Per your comment in v10, such movement may avoid false cacheline conflicts.
> >> > The comment is below.
> >> >     Also please try to space apart the two locks, to avoid false cacheline
> >> >     conflicts (e.g. the new lock may well go immediately before the array
> >> >     it pairs with).
> >> 
> >> Well - where is the second lock here?
> >> 
> > I thought 'feat_init' has same effect. But I should be wrong.
> > 
> > Then, I want to define the structure as below:
> > 
> > struct psr_socket_info {
> >     bool feat_init;
> >     /* Feature array's index is 'enum psr_feat_type' which is same as 'props' */
> >     struct feat_node *features[PSR_SOCKET_FEAT_NUM];
> >     spinlock_t ref_lock;
> >     unsigned int cos_ref[MAX_COS_REG_CNT];
> >     /* Every bit corresponds to a domain. Index is domain_id. */
> >     DECLARE_BITMAP(dom_ids, DOMID_IDLE + 1);
> > };
> 
> I've outlined my expectation to the ordering of fields before. The
> above broadly matches that, so would be fine. What I'd like to ask
> though is that fields don't get moved around without reason during
> the series. Insert new fields at their intended final place unless
> there's an actual reason to move them later.
> 
Ok, I will be careful about this to put the new field to its final
place when implement it.

> >> >> > + free_array:
> >> >> > +    xfree(val_array);
> >> >> > +    return ret;
> >> >> > +
> >> >> > + unlock_free_array:
> >> >> > +    spin_unlock(&info->ref_lock);
> >> >> > +    xfree(val_array);
> >> >> > +    return ret;
> >> >> > +}
> >> >> 
> >> >> I'm sure I've said so before - please don't duplicate error paths like
> >> >> this. Here it's still easy to see all is fine, but what if each path gets
> >> >> two or three more thing added. Please chain them together via goto.
> >> >> 
> >> > To make things clear, I wrote below codes. How about them?
> >> >  unlock_free_array:
> >> >     spin_unlock(&info->ref_lock);
> >> > 
> >> >  free_array:
> >> >     xfree(val_array);
> >> >     return ret;
> >> 
> >> I don't think that'll be okay for the case which previously fell
> >> through to free_array.
> >> 
> > I tried to understand your meaning. Do you mean below codes?
> > 
> >     set_bit(d->domain_id, info->dom_ids); //Success path.
> >     goto free_array;
> > 
> >  unlock_free_array:
> >     spin_unlock(&info->ref_lock);
> > 
> >  free_array:
> >     xfree(val_array);
> >     return ret;
> 
> Coming close: Once again, using "goto" on error paths is half way
> acceptable to me, while using it anywhere else normally isn't.
> Hence you want the "unlock_free_array" path "goto free_array;"
> rather than the normal (success) one. Alternatively you might use
> a local variable to signal whether to release the lock.
> 
How about this which can avoid a local variable?

    set_bit(d->domain_id, info->dom_ids);

 free_array:
    xfree(val_array);
    return ret;

 unlock_free_array:
    spin_unlock(&info->ref_lock);
    goto free_array;

> Jan

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  reply	other threads:[~2017-06-06  8:19 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-03  8:44 [PATCH v11 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-05-03  8:44 ` [PATCH v11 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-05-03  8:44 ` [PATCH v11 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-05-03  8:44 ` [PATCH v11 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-05-03  8:44 ` [PATCH v11 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-05-30 13:05   ` Jan Beulich
2017-05-31  2:44     ` Yi Sun
2017-05-31  6:02       ` Jan Beulich
2017-05-31  9:36   ` Jan Beulich
2017-06-01  3:18     ` Yi Sun
2017-06-01  6:57       ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-05-30 13:26   ` Jan Beulich
2017-05-31  6:37     ` Yi Sun
2017-05-31  6:57       ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-05-30 13:51   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-05-30 14:05   ` Jan Beulich
2017-05-31  7:30     ` Yi Sun
2017-05-31  7:45       ` Jan Beulich
2017-05-31  8:05         ` Yi Sun
2017-05-31  8:10           ` Jan Beulich
2017-06-01  3:14             ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-05-30 14:32   ` Jan Beulich
2017-06-01 10:00     ` Yi Sun
2017-06-01 10:45       ` Jan Beulich
2017-06-02  2:49         ` Yi Sun
2017-06-06  7:43           ` Jan Beulich
2017-06-06  8:18             ` Yi Sun [this message]
2017-06-06  8:39               ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-05-30 15:17   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-05-30 15:23   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-05-30 15:35   ` Jan Beulich
2017-06-05  8:10     ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 13/23] x86: refactor psr: CDP: implement CPU init flow Yi Sun
2017-05-31  9:37   ` Jan Beulich
2017-06-02  7:26     ` Yi Sun
2017-06-06  7:45       ` Jan Beulich
2017-06-06  8:13         ` Yi Sun
2017-06-06  8:38           ` Jan Beulich
2017-06-07  1:31             ` Yi Sun
2017-06-07  7:28               ` Yi Sun
2017-06-07  8:14               ` Jan Beulich
2017-06-07  9:00                 ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-05-31  9:40   ` Jan Beulich
2017-06-05  8:09     ` Yi Sun
2017-05-03  8:44 ` [PATCH v11 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-05-31  9:44   ` Jan Beulich
2017-06-02  7:59     ` Yi Sun
2017-06-06  7:48       ` Jan Beulich
2017-06-06  8:22         ` Yi Sun
2017-06-06  8:43           ` Jan Beulich
2017-06-06 10:43             ` Yi Sun
2017-06-06 10:49               ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-05-03  8:44 ` [PATCH v11 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-05-31  9:51   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 19/23] x86: L2 CAT: implement set " Yi Sun
2017-05-31  9:52   ` Jan Beulich
2017-05-03  8:44 ` [PATCH v11 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-05-11 12:39   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-05-11 12:40   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 22/23] tools: L2 CAT: support set " Yi Sun
2017-05-11 12:43   ` Wei Liu
2017-05-03  8:44 ` [PATCH v11 23/23] docs: add L2 CAT description in docs Yi Sun

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