From: Yi Sun <yi.y.sun@linux.intel.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
he.chen@linux.intel.com, andrew.cooper3@citrix.com,
dario.faggioli@citrix.com, ian.jackson@eu.citrix.com,
mengxu@cis.upenn.edu, chao.p.peng@linux.intel.com,
xen-devel@lists.xenproject.org, roger.pau@citrix.com
Subject: Re: [PATCH v12 15/23] x86: refactor psr: CDP: implement set value callback function.
Date: Mon, 3 Jul 2017 14:33:03 +0800 [thread overview]
Message-ID: <20170703063302.GN3420@yi.y.sun> (raw)
In-Reply-To: <59563DD8020000780010194F@prv-mh.provo.novell.com>
On 17-06-30 06:02:32, Jan Beulich wrote:
> >>> Yi Sun <yi.y.sun@linux.intel.com> 06/30/17 1:30 PM >>>
> >The input 'type' is CODE. The props->type[0] is DATA and props->type[1] is CODE.
> >In the first iteration, the props->type[0] is DATA so that it does not match
> >'type' and the second check is false too. If we use else branch here, it will
> >enter the branch and return -EVINVAL. But this is not we want, right? We hope
> >the second iteration should be executed to set CODE.
>
> I see. That'll then call for yet another solution; I don't think the code should
> stay as is.
>
Then, how about ASSERT() at the beginning to check if input 'type' is correct?
enum cbm_type {
PSR_CBM_TYPE_L3,
PSR_CBM_TYPE_L3_DATA,
PSR_CBM_TYPE_L3_CODE,
PSR_CBM_TYPE_L2,
};
ASSERT((type >= props->type[0] && type <= props->type[props->cos_num - 1]) ||
type == props->alt_type);
We don't need 'ret' anymore with above check.
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next prev parent reply other threads:[~2017-07-03 6:33 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-14 1:12 [PATCH v12 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c Yi Sun
2017-06-14 1:12 ` [PATCH v12 01/23] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document Yi Sun
2017-06-14 1:12 ` [PATCH v12 02/23] x86: move cpuid_count_leaf from cpuid.c to processor.h Yi Sun
2017-06-14 1:12 ` [PATCH v12 03/23] x86: refactor psr: remove L3 CAT/CDP codes Yi Sun
2017-06-14 1:12 ` [PATCH v12 04/23] x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows Yi Sun
2017-06-28 7:12 ` Jan Beulich
2017-06-28 9:07 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 05/23] x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows Yi Sun
2017-06-28 7:13 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 06/23] x86: refactor psr: L3 CAT: implement get hw info flow Yi Sun
2017-06-14 1:12 ` [PATCH v12 07/23] x86: refactor psr: L3 CAT: implement get value flow Yi Sun
2017-06-28 7:14 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 08/23] x86: refactor psr: L3 CAT: set value: implement framework Yi Sun
2017-06-28 7:14 ` Jan Beulich
2017-06-28 9:09 ` Yi Sun
2017-06-28 11:43 ` Jan Beulich
2017-06-29 5:12 ` Yi Sun
2017-06-29 6:24 ` Jan Beulich
2017-06-29 7:21 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 09/23] x86: refactor psr: L3 CAT: set value: assemble features value array Yi Sun
2017-06-29 17:56 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 10/23] x86: refactor psr: L3 CAT: set value: implement cos finding flow Yi Sun
2017-06-29 17:57 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 11/23] x86: refactor psr: L3 CAT: set value: implement cos id picking flow Yi Sun
2017-06-29 17:59 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 12/23] x86: refactor psr: L3 CAT: set value: implement write msr flow Yi Sun
2017-06-29 18:00 ` Jan Beulich
2017-06-30 5:45 ` Yi Sun
2017-06-30 6:45 ` Jan Beulich
2017-06-30 7:08 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 13/23] x86: refactor psr: CDP: implement CPU init flow Yi Sun
2017-06-30 6:40 ` Jan Beulich
2017-06-30 6:59 ` Yi Sun
2017-06-30 7:33 ` Jan Beulich
2017-06-30 8:04 ` Yi Sun
2017-06-30 9:18 ` Jan Beulich
2017-07-04 1:40 ` Yi Sun
2017-07-04 7:28 ` Jan Beulich
2017-07-05 1:45 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 14/23] x86: refactor psr: CDP: implement get hw info flow Yi Sun
2017-06-30 6:41 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 15/23] x86: refactor psr: CDP: implement set value callback function Yi Sun
2017-06-30 6:42 ` Jan Beulich
2017-06-30 7:22 ` Yi Sun
2017-06-30 8:54 ` Yi Sun
2017-06-30 9:33 ` Jan Beulich
2017-06-30 11:29 ` Yi Sun
2017-06-30 12:02 ` Jan Beulich
2017-07-03 6:33 ` Yi Sun [this message]
2017-07-03 7:01 ` Jan Beulich
2017-07-03 8:40 ` Yi Sun
2017-07-03 9:18 ` Jan Beulich
2017-07-03 12:52 ` Yi Sun
2017-07-03 13:02 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 16/23] x86: L2 CAT: implement CPU init flow Yi Sun
2017-06-30 6:58 ` Jan Beulich
2017-06-30 7:27 ` Yi Sun
2017-06-30 7:36 ` Jan Beulich
2017-06-30 8:05 ` Yi Sun
2017-06-14 1:12 ` [PATCH v12 17/23] x86: L2 CAT: implement get hw info flow Yi Sun
2017-06-30 6:59 ` Jan Beulich
2017-06-14 1:12 ` [PATCH v12 18/23] x86: L2 CAT: implement get value flow Yi Sun
2017-06-14 1:12 ` [PATCH v12 19/23] x86: L2 CAT: implement set " Yi Sun
2017-06-14 1:12 ` [PATCH v12 20/23] tools: L2 CAT: support get HW info for L2 CAT Yi Sun
2017-06-14 1:12 ` [PATCH v12 21/23] tools: L2 CAT: support show cbm " Yi Sun
2017-06-14 1:12 ` [PATCH v12 22/23] tools: L2 CAT: support set " Yi Sun
2017-06-14 1:12 ` [PATCH v12 23/23] docs: add L2 CAT description in docs Yi Sun
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