[PATCH v3 0/3] Rework vlapic timer to behave more like real-hardware

[Anthony PERARD <anthony.perard@citrix.com>]

Hi,

When developing PVH for OVMF, I've used the lapic timer. It turns out that the
way it is used by OVMF did not work with Xen [1]. I tried to find out how
real-hw behave, and write a XTF tests [2]. And this patch series tries to fix
the behavior of the vlapic timer.

The OVMF driver for the APIC timer initialize the timer like this:
  write to TMICT (initial counter)
  write to TMDCR (divide configuration)
  enable the timer (this may change timer mode from one-shot to periodic)
It turns out that TMICT is set to 0 on the last step, but OVMF expect the timer
to run.

Here is some description of the APIC timer, base on observation as well as read
of the Intel SDM. The description is also patch of patch description
(reworded).

Maybe a way of thinking how the APIC timer is evaluated, is to think of how
hardward will do it. There is a counter TMCCT which always keeps counting down.

Setting TMICT also set TMCCT, nothing else matter.
Setting LVTT does not change anything right away.
Setting TMDCR does not change much.

Now TMCCT keeps counting down, by a value related to TMDCR.
Once, TMCCT reach 0, it is only at this time that LVTT is taken into account.
Is there an interrupt to deliver? Should the timer restart counting from the
value in TMICT?

In the Intel SDM, there is the word "disarm" of the timer used. I guess the
easier way to disarm the APIC timer (when in periodic or one-shot) is to set
TMICT to 0. But if we take TSC-Deadline mode out of the picture, there is
nothing in the manual that say that the timer is disarm or stopped when
changing timer mode (there is only two modes left, period and one-shot).

As for the TSC-deadline timer mode, observation shown that changing to it (or
from it) does reset and disarm both timers, so effectively TMICT and the
tscdeadline are set to 0.

There is a XTF patch series that check the emulation of the vlapic timer.
"[XTF PATCH V2 0/3] Testing vlapic timer"

This patch series can be found at:
https://xenbits.xen.org/git-http/people/aperard/xen-unstable.git
tag: vlapic-timer-v3

Changes in V3:
- details in patches.

Changes in V2:
- patches have been reworked.
- vlapic_update_timer does not care anymore which register is been changed.
- more comments, hopefully also better.

Thanks,

[1] https://lists.xenproject.org/archives/html/xen-devel/2016-12/msg00959.html
[2] v1: https://lists.xenproject.org/archives/html/xen-devel/2017-03/msg02533.html
    v2: look for "[XTF PATCH V2 0/3] Testing vlapic timer"

Anthony PERARD (3):
  x86/vlapic: Introduce vlapic_update_timer
  x86/vlapic: Keep timer running when switching between one-shot and
    periodic mode
  x86/vlapic: Apply change to TDCR right away to the timer

 xen/arch/x86/hvm/vlapic.c | 126 ++++++++++++++++++++++++++++++++++------------
 1 file changed, 94 insertions(+), 32 deletions(-)

-- 
Anthony PERARD


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