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From: Yi Sun <yi.y.sun@linux.intel.com>
To: "Roger Pau Monn�" <roger.pau@citrix.com>
Cc: kevin.tian@intel.com, wei.liu2@citrix.com,
	andrew.cooper3@citrix.com, dario.faggioli@citrix.com,
	ian.jackson@eu.citrix.com, julien.grall@arm.com,
	mengxu@cis.upenn.edu, jbeulich@suse.com,
	chao.p.peng@linux.intel.com, xen-devel@lists.xenproject.org,
	dgdegra@tycho.nsa.gov
Subject: Re: [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA
Date: Wed, 20 Sep 2017 11:22:58 +0800	[thread overview]
Message-ID: <20170920032258.GF11006@yi.y.sun> (raw)
In-Reply-To: <20170919085528.lovtryjfkor3by5l@dhcp-3-128.uk.xensource.com>

On 17-09-19 09:55:28, Roger Pau Monn� wrote:
> On Tue, Sep 05, 2017 at 05:32:26PM +0800, Yi Sun wrote:
> > This patch implements main data structures of MBA.
> > 
> > Like CAT features, MBA HW info has cos_max which means the max thrtl
> > register number, and thrtl_max which means the max throttle value
> > (delay value). It also has a flag to represent if the throttle
> > value is linear or not.
> > 
> > One thrtl register of MBA stores a throttle value for one or more
> > domains. The throttle value means the transaction time between L2
> > cache and next level memory to be delayed.
> 
> "The throttle value contains the delay between L2 cache and the next
> cache level."
> 
> Seems better, but I'm not a native speaker anyway.
> 
Or:
"The throttle value means the delay between L2 cache and the next cache level."

[...]

> >  struct feat_node {
> > -    /* cos_max and cbm_len are common values for all features so far. */
> > +    /* cos_max is common values for all features so far. */
> 
> ...common among all features...
> 
Ok, thanks!

[...]

> > +static int mba_init_feature(const struct cpuid_leaf *regs,
> > +                            struct feat_node *feat,
> > +                            struct psr_socket_info *info,
> > +                            enum psr_feat_type type)
> > +{
> > +    /* No valid value so do not enable feature. */
> > +    if ( !regs->a || !regs->d )
> > +        return -ENOENT;
> > +
> > +    if ( type != FEAT_TYPE_MBA )
> > +        return -ENOENT;
> 
> You can join the two checks above in a single if.
> 
Sure.

> > +
> > +    feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
> > +    if ( feat->cos_max < 1 )
> > +        return -ENOENT;
> > +
> > +    feat->mba.thrtl_max = (regs->a & MBA_THRTL_MAX_MASK) + 1;
> > +
> > +    if ( regs->c & MBA_LINEAR_MASK )
> > +    {
> > +        feat->mba.linear = true;
> > +
> > +        if ( feat->mba.thrtl_max >= 100 )
> > +            return -ENOENT;
> > +    }
> > +
> > +    /* We reserve cos=0 as default thrtl (0) which means no delay. */
> > +    feat->cos_reg_val[0] = 0;
> 
> AFAICT feat is allocated using xzalloc, so this will already be 0.
> 
Yes, you are right. My original purpose is to explicitly let reader know that
'cos=0' is reserved. But the code is redundant that I will remove it.

> > @@ -1389,6 +1480,7 @@ static void psr_cpu_init(void)
> >      unsigned int socket, cpu = smp_processor_id();
> >      struct feat_node *feat;
> >      struct cpuid_leaf regs;
> > +    uint32_t reg_b;
> 
> Not sure of the benefit between using regs.b or reg_b (it's only 1
> char shorter).
> 
You can see the 'regs' is overwritten in below codes so that the 'regs.b' is not
kept. To add a new local variable 'reg_b' here, we can avoid calling
'cpuid_count_leaf' for L2 CAT and MBA.

> >  
> >      if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) )
> >          goto assoc_init;
> > @@ -1407,7 +1499,8 @@ static void psr_cpu_init(void)
> >      spin_lock_init(&info->ref_lock);
> >  
> >      cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, &regs);
> > -    if ( regs.b & PSR_RESOURCE_TYPE_L3 )
> > +    reg_b = regs.b;
> > +    if ( reg_b & PSR_RESOURCE_TYPE_L3 )
> >      {
> >          cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, &regs);
> >  
> > @@ -1428,8 +1521,7 @@ static void psr_cpu_init(void)
> >          }
> >      }
> >  
> > -    cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, &regs);
> > -    if ( regs.b & PSR_RESOURCE_TYPE_L2 )
> > +    if ( reg_b & PSR_RESOURCE_TYPE_L2 )
> >      {
> >          cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, &regs);
> >  
> > @@ -1441,6 +1533,18 @@ static void psr_cpu_init(void)
> >              feat_l2_cat = feat;
> >      }
> >  
> > +    if ( reg_b & PSR_RESOURCE_TYPE_MBA )
> > +    {
> > +        cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, &regs);
> > +
> > +        feat = feat_mba;
> > +        feat_mba = NULL;
> > +        if ( !mba_init_feature(&regs, feat, info, FEAT_TYPE_MBA) )
> 
> Seems kind of pointless that mba_init_feature returns an error code
> when it's ignored by it's callers. You could switch it to bool if you
> are going to use it like that.
> 
Hmm, bool type seems better. Thanks!

> Thanks, Roger.

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  reply	other threads:[~2017-09-20  3:24 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-05  9:32 [PATCH v3 00/15] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-09-05  9:32 ` [PATCH v3 01/15] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-09-18 17:16   ` Roger Pau Monné
2017-09-19  6:07     ` Jan Beulich
2017-09-20  2:59       ` Yi Sun
2017-09-20  3:06     ` Yi Sun
2017-09-20  8:36       ` Roger Pau Monné
2017-09-20  9:08         ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 02/15] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-09-19  8:03   ` Roger Pau Monné
2017-09-20  3:12     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 03/15] x86: rename 'cbm_type' to 'psr_type' to make it general Yi Sun
2017-09-19  8:22   ` Roger Pau Monné
2017-09-05  9:32 ` [PATCH v3 04/15] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-09-19  8:55   ` Roger Pau Monné
2017-09-20  3:22     ` Yi Sun [this message]
2017-09-20  7:11       ` Jan Beulich
2017-09-20  7:27         ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 05/15] x86: implement get hw info " Yi Sun
2017-09-19  9:08   ` Roger Pau Monné
2017-09-20  5:05     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 06/15] x86: implement get value interface " Yi Sun
2017-09-19  9:15   ` Roger Pau Monné
2017-09-20  5:09     ` Yi Sun
2017-09-20  8:43       ` Roger Pau Monné
2017-09-20  9:22         ` Yi Sun
2017-09-20 16:02           ` Wei Liu
2017-09-05  9:32 ` [PATCH v3 07/15] x86: implement set value flow " Yi Sun
2017-09-19  9:57   ` Roger Pau Monné
2017-09-20  5:39     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 08/15] tools: create general interfaces to support psr allocation features Yi Sun
2017-09-19 10:04   ` Roger Pau Monné
2017-09-20  5:45     ` Yi Sun
2017-09-22  7:01     ` Chao Peng
2017-09-28 16:11       ` Wei Liu
2017-09-05  9:32 ` [PATCH v3 09/15] tools: implement the new libxc get hw info interface Yi Sun
2017-09-19 10:15   ` Roger Pau Monné
2017-09-20  6:13     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 10/15] tools: implement the new libxl " Yi Sun
2017-09-19 10:28   ` Roger Pau Monné
2017-09-20  6:20     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 11/15] tools: implement the new xl " Yi Sun
2017-09-19 10:32   ` Roger Pau Monné
2017-09-20  6:23     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 12/15] tools: rename 'xc_psr_cat_type' to 'xc_psr_type' Yi Sun
2017-09-19 10:34   ` Roger Pau Monné
2017-09-20  6:25     ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 13/15] tools: implement new generic get value interface and MBA get value command Yi Sun
2017-09-19 11:02   ` Roger Pau Monné
2017-09-20  6:46     ` Yi Sun
2017-09-20  8:57       ` Roger Pau Monné
2017-09-20  9:11         ` Yi Sun
2017-09-05  9:32 ` [PATCH v3 14/15] tools: implement new generic set value interface and MBA set " Yi Sun
2017-09-19 11:30   ` Roger Pau Monné
2017-09-20  7:25     ` Yi Sun
2017-09-20 16:10     ` Wei Liu
2017-09-28 16:23       ` Dario Faggioli
2017-09-29 12:58         ` Wei Liu
2017-09-05  9:32 ` [PATCH v3 15/15] docs: add MBA description in docs Yi Sun
2017-09-19 11:37   ` Roger Pau Monné
2017-09-20  7:26     ` Yi Sun
2017-09-28 16:56     ` Dario Faggioli

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