From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Haozhong Zhang <haozhong.zhang@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>, xen-devel@lists.xen.org
Subject: Re: [PATCH] vt-d: use two 32-bit writes to update DMAR fault address registers
Date: Wed, 20 Sep 2017 09:31:19 +0100 [thread overview]
Message-ID: <20170920083119.xecn5v4svn3l6f5t@dhcp-3-128.uk.xensource.com> (raw)
In-Reply-To: <20170911060048.24571-1-haozhong.zhang@intel.com>
On Mon, Sep 11, 2017 at 02:00:48PM +0800, Haozhong Zhang wrote:
> The 64-bit DMAR fault address is composed of two 32 bits registers
> DMAR_FEADDR_REG and DMAR_FEUADDR_REG. According to VT-d spec:
> "Software is expected to access 32-bit registers as aligned doublewords",
> a hypervisor should use two 32-bit writes to DMAR_FEADDR_REG and
> DMAR_FEUADDR_REG separately in order to update a 64-bit fault address,
> rather than a 64-bit write to DMAR_FEADDR_REG.
I would add:
"Note that when x2APIC is disabled DMAR_FEUADDR_REG is reserved and it's not
necessary to update it."
> Though I haven't seen any errors caused by such one 64-bit write on
> real machines, it's still better to follow the specification.
>
> Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Given the reply from Kevin:
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Thanks, Roger.
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next prev parent reply other threads:[~2017-09-20 8:31 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-11 6:00 [PATCH] vt-d: use two 32-bit writes to update DMAR fault address registers Haozhong Zhang
2017-09-11 9:38 ` Roger Pau Monné
2017-09-11 12:13 ` Haozhong Zhang
2017-09-18 8:14 ` Tian, Kevin
2017-09-11 10:02 ` Jan Beulich
2017-09-18 8:18 ` Tian, Kevin
2017-09-18 8:30 ` Jan Beulich
2017-09-18 9:05 ` Haozhong Zhang
2017-09-18 9:10 ` Roger Pau Monné
2017-09-20 2:48 ` Tian, Kevin
2017-09-20 8:31 ` Roger Pau Monné [this message]
2017-10-10 5:36 ` Tian, Kevin
2017-10-10 5:40 ` Zhang, Haozhong
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