From mboxrd@z Thu Jan 1 00:00:00 1970 From: Haozhong Zhang Subject: [PATCH v2] VT-d: use two 32-bit writes to update DMAR fault address registers Date: Wed, 11 Oct 2017 11:03:45 +0800 Message-ID: <20171011030345.14408-1-haozhong.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel@lists.xen.org Cc: Andrew Cooper , Kevin Tian , Haozhong Zhang , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= List-Id: xen-devel@lists.xenproject.org VGhlIDY0LWJpdCBETUFSIGZhdWx0IGFkZHJlc3MgaXMgY29tcG9zZWQgb2YgdHdvIDMyIGJpdHMg cmVnaXN0ZXJzCkRNQVJfRkVBRERSX1JFRyBhbmQgRE1BUl9GRVVBRERSX1JFRy4gQWNjb3JkaW5n IHRvIFZULWQgc3BlYzoKIlNvZnR3YXJlIGlzIGV4cGVjdGVkIHRvIGFjY2VzcyAzMi1iaXQgcmVn aXN0ZXJzIGFzIGFsaWduZWQgZG91Ymxld29yZHMiLAphIGh5cGVydmlzb3Igc2hvdWxkIHVzZSB0 d28gMzItYml0IHdyaXRlcyB0byBETUFSX0ZFQUREUl9SRUcgYW5kCkRNQVJfRkVVQUREUl9SRUcg c2VwYXJhdGVseSBpbiBvcmRlciB0byB1cGRhdGUgYSA2NC1iaXQgZmF1bHQgYWRkcmVzcywKcmF0 aGVyIHRoYW4gYSA2NC1iaXQgd3JpdGUgdG8gRE1BUl9GRUFERFJfUkVHLiBOb3RlIHRoYXQgd2hl biB4MkFQSUMKaXMgbm90IGVuYWJsZWQgRE1BUl9GRVVBRERSX1JFRyBpcyByZXNlcnZlZCBhbmQg aXQncyBub3QgbmVjZXNzYXJ5IHRvCnVwZGF0ZSBpdC4KClRob3VnaCBJIGhhdmVuJ3Qgc2VlbiBh bnkgZXJyb3JzIGNhdXNlZCBieSBzdWNoIG9uZSA2NC1iaXQgd3JpdGUgb24KcmVhbCBtYWNoaW5l cywgaXQncyBzdGlsbCBiZXR0ZXIgdG8gZm9sbG93IHRoZSBzcGVjaWZpY2F0aW9uLgoKRml4ZXM6 IGFlMDVmZDM5MTJiICgiVlQtZDogdXNlIHF3b3JkIE1NSU8gYWNjZXNzIGZvciBNU0kgYWRkcmVz cyB3cml0ZXMiKQpSZXZpZXdlZC1ieTogUm9nZXIgUGF1IE1vbm7DqSA8cm9nZXIucGF1QGNpdHJp eC5jb20+ClNpZ25lZC1vZmYtYnk6IEhhb3pob25nIFpoYW5nIDxoYW96aG9uZy56aGFuZ0BpbnRl bC5jb20+Ci0tLQpDaGFuZ2VzIGluIHYyOgogKiBFeHBsYWluIGluIGNvbW1pdCBtZXNzYWdlIGFu ZCBjb2RlIGNvbW1lbnQgd2h5IG5vdCB1cGRhdGluZyBETUFSX0ZFVUFERFJfUkVHCiAgIHdoZW4g eDJBUElDIGlzIG5vdCBlbmFibGVkCgpUaGlzIHBhdGNoIGFjdHVhbGx5IHJldmVydHMgcGFydCBv ZiBjb21taXQgYWUwNWZkMzkxMmIKKCJWVC1kOiB1c2UgcXdvcmQgTU1JTyBhY2Nlc3MgZm9yIE1T SSBhZGRyZXNzIHdyaXRlcyIpLiBUaGUgbGF0dGVyCndhcyBpbmNsdWRlZCBpbiBYU0EtMTIwLCAx MjguLjEzMSBmb2xsb3ctdXAgcGF0Y2ggc2VyaWVzIFsxXS4gSQpkb24ndCBrbm93IHdoZXRoZXIg bXkgcGF0Y2ggYnJlYWtzIHRob3NlIFhTQSBmaXhlcy4gSWYgaXQgZG9lcywKcGxlYXNlIGRyb3Ag bXkgcGF0Y2guCgpbMV0gaHR0cHM6Ly9saXN0cy54ZW5wcm9qZWN0Lm9yZy9hcmNoaXZlcy9odG1s L3hlbi1kZXZlbC8yMDE1LTA2L21zZzAwNjM4Lmh0bWwKLS0tCiB4ZW4vZHJpdmVycy9wYXNzdGhy b3VnaC92dGQvaW9tbXUuYyB8IDggKysrKysrKy0KIDEgZmlsZSBjaGFuZ2VkLCA3IGluc2VydGlv bnMoKyksIDEgZGVsZXRpb24oLSkKCmRpZmYgLS1naXQgYS94ZW4vZHJpdmVycy9wYXNzdGhyb3Vn aC92dGQvaW9tbXUuYyBiL3hlbi9kcml2ZXJzL3Bhc3N0aHJvdWdoL3Z0ZC9pb21tdS5jCmluZGV4 IGRhYWVkMGFiYmQuLjgxZGQyMDg1YzcgMTAwNjQ0Ci0tLSBhL3hlbi9kcml2ZXJzL3Bhc3N0aHJv dWdoL3Z0ZC9pb21tdS5jCisrKyBiL3hlbi9kcml2ZXJzL3Bhc3N0aHJvdWdoL3Z0ZC9pb21tdS5j CkBAIC0xMTA1LDcgKzExMDUsMTMgQEAgc3RhdGljIHZvaWQgZG1hX21zaV9zZXRfYWZmaW5pdHko c3RydWN0IGlycV9kZXNjICpkZXNjLCBjb25zdCBjcHVtYXNrX3QgKm1hc2spCiAKICAgICBzcGlu X2xvY2tfaXJxc2F2ZSgmaW9tbXUtPnJlZ2lzdGVyX2xvY2ssIGZsYWdzKTsKICAgICBkbWFyX3dy aXRlbChpb21tdS0+cmVnLCBETUFSX0ZFREFUQV9SRUcsIG1zZy5kYXRhKTsKLSAgICBkbWFyX3dy aXRlcShpb21tdS0+cmVnLCBETUFSX0ZFQUREUl9SRUcsIG1zZy5hZGRyZXNzKTsKKyAgICBkbWFy X3dyaXRlbChpb21tdS0+cmVnLCBETUFSX0ZFQUREUl9SRUcsIG1zZy5hZGRyZXNzX2xvKTsKKyAg ICAvKgorICAgICAqIFdoZW4geDJBUElDIGlzIG5vdCBlbmFibGVkLCBETUFSX0ZFVUFERFJfUkVH IGlzIHJlc2VydmVkIGFuZAorICAgICAqIGl0J3Mgbm90IG5lY2Vzc2FyeSB0byB1cGRhdGUgaXQu CisgICAgICovCisgICAgaWYgKHgyYXBpY19lbmFibGVkKQorICAgICAgICBkbWFyX3dyaXRlbChp b21tdS0+cmVnLCBETUFSX0ZFVUFERFJfUkVHLCBtc2cuYWRkcmVzc19oaSk7CiAgICAgc3Bpbl91 bmxvY2tfaXJxcmVzdG9yZSgmaW9tbXUtPnJlZ2lzdGVyX2xvY2ssIGZsYWdzKTsKIH0KIAotLSAK Mi4xMS4wCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K WGVuLWRldmVsIG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xp c3RzLnhlbi5vcmcveGVuLWRldmVsCg==