From: Chao Gao <chao.gao@intel.com>
To: "Roger Pau Monné" <roger.pau@citrix.com>
Cc: Lan Tianyu <tianyu.lan@intel.com>,
andrew.cooper3@citrix.com, kevin.tian@intel.com,
jbeulich@suse.com, xen-devel@lists.xen.org
Subject: Re: [PATCH V3 26/29] x86/vvtd: Handle interrupt translation faults
Date: Fri, 20 Oct 2017 13:54:15 +0800 [thread overview]
Message-ID: <20171020055415.GK74825@op-computing> (raw)
In-Reply-To: <20171019163137.ozlz4mx5mn4wmtzb@dhcp-3-128.uk.xensource.com>
On Thu, Oct 19, 2017 at 05:31:37PM +0100, Roger Pau Monné wrote:
>On Thu, Sep 21, 2017 at 11:02:07PM -0400, Lan Tianyu wrote:
>> From: Chao Gao <chao.gao@intel.com>
>>
>> Interrupt translation faults are non-recoverable fault. When faults
>> are triggered, it needs to populate fault info to Fault Recording
>> Registers and inject vIOMMU msi interrupt to notify guest IOMMU driver
>> to deal with faults.
>>
>> This patch emulates hardware's handling interrupt translation
>> faults (more information about the process can be found in VT-d spec,
>> chipter "Translation Faults", section "Non-Recoverable Fault
>> Reporting" and section "Non-Recoverable Logging").
>> Specifically, viommu_record_fault() records the fault information and
>> viommu_report_non_recoverable_fault() reports faults to software.
>> Currently, only Primary Fault Logging is supported and the Number of
>> Fault-recording Registers is 1.
>>
>> Signed-off-by: Chao Gao <chao.gao@intel.com>
>> Signed-off-by: Lan Tianyu <tianyu.lan@intel.com>
>> ---
>> xen/drivers/passthrough/vtd/iommu.h | 60 +++++++--
>> xen/drivers/passthrough/vtd/vvtd.c | 252 +++++++++++++++++++++++++++++++++++-
>> 2 files changed, 301 insertions(+), 11 deletions(-)
>>
>> diff --git a/xen/drivers/passthrough/vtd/iommu.h b/xen/drivers/passthrough/vtd/iommu.h
>> index 790384f..e19b045 100644
>> --- a/xen/drivers/passthrough/vtd/iommu.h
>> +++ b/xen/drivers/passthrough/vtd/iommu.h
>> @@ -198,26 +198,66 @@
>> #define DMA_CCMD_CAIG_MASK(x) (((u64)x) & ((u64) 0x3 << 59))
>>
>> /* FECTL_REG */
>> -#define DMA_FECTL_IM (((u64)1) << 31)
>> +#define DMA_FECTL_IM_SHIFT 31
>> +#define DMA_FECTL_IM (1U << DMA_FECTL_IM_SHIFT)
>> +#define DMA_FECTL_IP_SHIFT 30
>> +#define DMA_FECTL_IP (1U << DMA_FECTL_IP_SHIFT)
>
>Is it fine to change those from uint64_t to unsigned int?
Yes. The FECTL and FSTS are 32-bit registers.
>
>>
>> /* FSTS_REG */
>> -#define DMA_FSTS_PFO ((u64)1 << 0)
>> -#define DMA_FSTS_PPF ((u64)1 << 1)
>> -#define DMA_FSTS_AFO ((u64)1 << 2)
>> -#define DMA_FSTS_APF ((u64)1 << 3)
>> -#define DMA_FSTS_IQE ((u64)1 << 4)
>> -#define DMA_FSTS_ICE ((u64)1 << 5)
>> -#define DMA_FSTS_ITE ((u64)1 << 6)
>> -#define DMA_FSTS_FAULTS DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_AFO | DMA_FSTS_APF | DMA_FSTS_IQE | DMA_FSTS_ICE | DMA_FSTS_ITE
>> +#define DMA_FSTS_PFO_SHIFT 0
>> +#define DMA_FSTS_PFO (1U << DMA_FSTS_PFO_SHIFT)
>> +#define DMA_FSTS_PPF_SHIFT 1
>> +#define DMA_FSTS_PPF (1U << DMA_FSTS_PPF_SHIFT)
>> +#define DMA_FSTS_AFO (1U << 2)
>> +#define DMA_FSTS_APF (1U << 3)
>> +#define DMA_FSTS_IQE (1U << 4)
>> +#define DMA_FSTS_ICE (1U << 5)
>> +#define DMA_FSTS_ITE (1U << 6)
>
>This seemingly non-functional changes should be done in a separate
>patch.
sure.
>> +static int vvtd_alloc_frcd(struct vvtd *vvtd)
>> +{
>> + int prev;
>> + uint64_t cap = vvtd_get_reg(vvtd, DMAR_CAP_REG);
>> + unsigned int base = cap_fault_reg_offset(cap);
>> +
>> + /* Set the F bit to indicate the FRCD is in use. */
>> + if ( !vvtd_test_and_set_bit(vvtd,
>> + base + vvtd->status.fault_index * DMA_FRCD_LEN +
>> + DMA_FRCD3_OFFSET, DMA_FRCD_F_SHIFT) )
>> + {
>> + prev = vvtd->status.fault_index;
>> + vvtd->status.fault_index = (prev + 1) % cap_num_fault_regs(cap);
>> + return vvtd->status.fault_index;
>
>I would prefer that you return the index as an unsigned int parameter
>passed by reference rather than as the return value of the function,
>but that might not be the preference of others.
What are the pros and cons?
>> +static int vvtd_record_fault(struct vvtd *vvtd,
>> + struct arch_irq_remapping_request *request,
>> + int reason)
>> +{
>> + struct vtd_fault_record_register frcd;
>> + int fault_index;
>> +
>> + switch(reason)
>> + {
>> + case VTD_FR_IR_REQ_RSVD:
>> + case VTD_FR_IR_INDEX_OVER:
>> + case VTD_FR_IR_ENTRY_P:
>> + case VTD_FR_IR_ROOT_INVAL:
>> + case VTD_FR_IR_IRTE_RSVD:
>> + case VTD_FR_IR_REQ_COMPAT:
>> + case VTD_FR_IR_SID_ERR:
>> + if ( vvtd_test_bit(vvtd, DMAR_FSTS_REG, DMA_FSTS_PFO_SHIFT) )
>> + return X86EMUL_OKAY;
>> +
>> + /* No available Fault Record means Fault overflowed */
>> + fault_index = vvtd_alloc_frcd(vvtd);
>> + if ( fault_index == -1 )
>
>Erm, wouldn't vvtd_alloc_frcd return -ENOMEM in case of error? Ie: you
>should check if ( fault_index < 0 ).
It is a mistake.
Thanks
Chao
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next prev parent reply other threads:[~2017-10-20 5:54 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-22 3:01 [PATCH V3 00/29] Lan Tianyu
2017-09-22 3:01 ` [PATCH V3 1/29] Xen/doc: Add Xen virtual IOMMU doc Lan Tianyu
2017-10-18 13:26 ` Roger Pau Monné
2017-10-19 2:26 ` Lan Tianyu
2017-10-19 8:49 ` Roger Pau Monné
2017-10-19 11:28 ` Jan Beulich
2017-10-24 7:16 ` Lan Tianyu
2017-09-22 3:01 ` [PATCH V3 2/29] VIOMMU: Add vIOMMU helper functions to create, destroy vIOMMU instance Lan Tianyu
2017-10-18 14:05 ` Roger Pau Monné
2017-10-19 6:31 ` Lan Tianyu
2017-10-19 8:47 ` Roger Pau Monné
2017-10-25 1:43 ` Lan Tianyu
2017-10-30 1:41 ` Lan Tianyu
2017-10-30 9:54 ` Roger Pau Monné
2017-10-30 1:51 ` Lan Tianyu
2017-11-06 8:19 ` Jan Beulich
2017-09-22 3:01 ` [PATCH V3 3/29] DOMCTL: Introduce new DOMCTL commands for vIOMMU support Lan Tianyu
2017-10-18 14:18 ` Roger Pau Monné
2017-10-19 6:41 ` Lan Tianyu
2017-09-22 3:01 ` [PATCH V3 4/29] tools/libacpi: Add DMA remapping reporting (DMAR) ACPI table structures Lan Tianyu
2017-10-18 14:36 ` Roger Pau Monné
2017-10-19 6:46 ` Lan Tianyu
2017-09-22 3:01 ` [PATCH V3 5/29] tools/libacpi: Add new fields in acpi_config for DMAR table Lan Tianyu
2017-10-18 15:12 ` Roger Pau Monné
2017-10-19 8:09 ` Lan Tianyu
2017-10-19 8:40 ` Roger Pau Monné
2017-10-25 6:06 ` Lan Tianyu
2017-10-19 11:31 ` Jan Beulich
2017-09-22 3:01 ` [PATCH V3 6/29] tools/libxl: Add a user configurable parameter to control vIOMMU attributes Lan Tianyu
2017-10-19 9:49 ` Roger Pau Monné
2017-10-20 1:36 ` Chao Gao
2017-09-22 3:01 ` [PATCH V3 7/29] tools/libxl: build DMAR table for a guest with one virtual VTD Lan Tianyu
2017-10-19 10:00 ` Roger Pau Monné
2017-10-20 1:44 ` Chao Gao
2017-09-22 3:01 ` [PATCH V3 8/29] tools/libxl: create vIOMMU during domain construction Lan Tianyu
2017-10-19 10:13 ` Roger Pau Monné
2017-10-26 12:05 ` Wei Liu
2017-10-27 1:58 ` Lan Tianyu
2017-09-22 3:01 ` [PATCH V3 9/29] tools/libxc: Add viommu operations in libxc Lan Tianyu
2017-10-19 10:17 ` Roger Pau Monné
2017-09-22 3:01 ` [PATCH V3 10/29] vtd: add and align register definitions Lan Tianyu
2017-10-19 10:21 ` Roger Pau Monné
2017-10-20 1:47 ` Chao Gao
2017-09-22 3:01 ` [PATCH V3 11/29] x86/hvm: Introduce a emulated VTD for HVM Lan Tianyu
2017-10-19 11:20 ` Roger Pau Monné
2017-10-20 2:46 ` Chao Gao
2017-10-20 6:56 ` Jan Beulich
2017-10-20 6:12 ` Chao Gao
2017-10-20 8:37 ` Lan Tianyu
2017-09-22 3:01 ` [PATCH V3 12/29] x86/vvtd: Add MMIO handler for VVTD Lan Tianyu
2017-10-19 11:34 ` Roger Pau Monné
2017-10-20 2:58 ` Chao Gao
2017-10-20 9:51 ` Roger Pau Monné
2017-09-22 3:01 ` [PATCH V3 13/29] x86/vvtd: Set Interrupt Remapping Table Pointer through GCMD Lan Tianyu
2017-10-19 11:56 ` Roger Pau Monné
2017-10-20 4:08 ` Chao Gao
2017-10-20 6:57 ` Jan Beulich
2017-09-22 3:01 ` [PATCH V3 14/29] x86/vvtd: Enable Interrupt Remapping " Lan Tianyu
2017-10-19 13:42 ` Roger Pau Monné
2017-09-22 3:01 ` [PATCH V3 15/29] x86/vvtd: Process interrupt remapping request Lan Tianyu
2017-10-19 14:26 ` Roger Pau Monné
2017-10-20 5:16 ` Chao Gao
2017-10-20 10:01 ` Roger Pau Monné
2017-10-23 6:44 ` Chao Gao
2017-09-22 3:01 ` [PATCH V3 16/29] x86/vvtd: decode interrupt attribute from IRTE Lan Tianyu
2017-10-19 14:39 ` Roger Pau Monné
2017-10-20 5:22 ` Chao Gao
2017-09-22 3:01 ` [PATCH V3 17/29] x86/vvtd: add a helper function to decide the interrupt format Lan Tianyu
2017-10-19 14:43 ` Roger Pau Monné
2017-09-22 3:01 ` [PATCH V3 18/29] VIOMMU: Add irq request callback to deal with irq remapping Lan Tianyu
2017-10-19 15:00 ` Roger Pau Monné
2017-09-22 3:02 ` [PATCH V3 19/29] x86/vioapic: Hook interrupt delivery of vIOAPIC Lan Tianyu
2017-10-19 15:37 ` Roger Pau Monné
2017-09-22 3:02 ` [PATCH V3 20/29] VIOMMU: Add get irq info callback to convert irq remapping request Lan Tianyu
2017-10-19 15:42 ` Roger Pau Monné
2017-10-25 7:30 ` Lan Tianyu
2017-10-25 7:43 ` Roger Pau Monné
2017-10-25 7:38 ` Lan Tianyu
2017-09-22 3:02 ` [PATCH V3 21/29] VIOMMU: Introduce callback of checking irq remapping mode Lan Tianyu
2017-10-19 15:43 ` Roger Pau Monné
2017-09-22 3:02 ` [PATCH V3 22/29] x86/vioapic: extend vioapic_get_vector() to support remapping format RTE Lan Tianyu
2017-10-19 15:49 ` Roger Pau Monné
2017-10-19 15:56 ` Jan Beulich
2017-10-20 1:04 ` Chao Gao
2017-09-22 3:02 ` [PATCH V3 23/29] passthrough: move some fields of hvm_gmsi_info to a sub-structure Lan Tianyu
2017-09-22 3:02 ` [PATCH V3 24/29] tools/libxc: Add a new interface to bind remapping format msi with pirq Lan Tianyu
2017-10-19 16:03 ` Roger Pau Monné
2017-10-20 5:39 ` Chao Gao
2017-09-22 3:02 ` [PATCH V3 25/29] x86/vmsi: Hook delivering remapping format msi to guest Lan Tianyu
2017-10-19 16:07 ` Roger Pau Monné
2017-10-20 6:48 ` Jan Beulich
2017-09-22 3:02 ` [PATCH V3 26/29] x86/vvtd: Handle interrupt translation faults Lan Tianyu
2017-10-19 16:31 ` Roger Pau Monné
2017-10-20 5:54 ` Chao Gao [this message]
2017-10-20 10:08 ` Roger Pau Monné
2017-10-20 14:20 ` Jan Beulich
2017-09-22 3:02 ` [PATCH V3 27/29] x86/vvtd: Enable Queued Invalidation through GCMD Lan Tianyu
2017-10-20 10:30 ` Roger Pau Monné
2017-09-22 3:02 ` [PATCH V3 28/29] x86/vvtd: Add queued invalidation (QI) support Lan Tianyu
2017-10-20 11:20 ` Roger Pau Monné
2017-10-23 7:50 ` Chao Gao
2017-10-23 8:57 ` Roger Pau Monné
2017-10-23 8:52 ` Chao Gao
2017-10-23 23:26 ` Tian, Kevin
2017-09-22 3:02 ` [PATCH V3 29/29] x86/vvtd: save and restore emulated VT-d Lan Tianyu
2017-10-20 11:25 ` Roger Pau Monné
2017-10-20 11:36 ` [PATCH V3 00/29] Roger Pau Monné
2017-10-23 1:23 ` Lan Tianyu
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