Re: [PATCH v3 3/4] x86emul: Support vaes insns

[Yang Zhong <yang.zhong@intel.com>]

On Mon, Nov 27, 2017 at 09:30:15AM -0700, Jan Beulich wrote:
> >>> On 10.11.17 at 11:36, <yang.zhong@intel.com> wrote:
> > --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> > @@ -1626,6 +1626,7 @@ static bool vcpu_has(
> >  #define vcpu_has_clwb()        vcpu_has(         7, EBX, 24, ctxt, ops)
> >  #define vcpu_has_sha()         vcpu_has(         7, EBX, 29, ctxt, ops)
> >  #define vcpu_has_gfni()        vcpu_has(         7, ECX,  8, ctxt, ops)
> > +#define vcpu_has_vaes()        vcpu_has(         7, ECX,  9, ctxt, ops)
> >  #define vcpu_has_vpclmulqdq()  vcpu_has(         7, ECX, 10, ctxt, ops)
> >  #define vcpu_has_rdpid()       vcpu_has(         7, ECX, 22, ctxt, ops)
> >  #define vcpu_has_clzero()      vcpu_has(0x80000008, EBX,  0, ctxt, ops)
> > @@ -7345,6 +7346,12 @@ x86_emulate(
> >          host_and_vcpu_must_have(aesni);
> >          if ( vex.opcx == vex_none )
> >              goto simd_0f38_common;
> > +        if ( vex.l )
> > +        {
> > +            host_and_vcpu_must_have(vaes);
> > +            goto simd_0f_avx;
> > +        }
> > +
> >          /* fall through */
> 
> Please move out the block no longer wanting this fall-through.
> That'll also take care of vaesimc not becoming 256-bit enabled as
> per the current version of the spec.
> 
  Hello Jan,

  Thanks for review patch!
  
  The new patch will like below:

      host_and_vcpu_must_have(aesni);
      if ( vex.opcx == vex_none )
          goto simd_0f38_common;
+     if ( !vex.l )
+         goto simd_0f_avx;  -----> this will deal with vaesimc insn
+     host_and_vcpu_must_have(vaes);
+     goto simd_0f_ymm;    ------> this will deal with 256 VEX insn

  I will also remove / * fall through */ comments here, thanks!

  Regards,

  Yang
  
> Jan

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel