[PATCH v2 08/30] hw/i386: use the BYTE-based definitions

[PATCH v2 08/30] hw/i386: use the BYTE-based definitions

[Philippe Mathieu-Daudé]

It eases code review, unit is explicit.

Patch generated using:

  $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/

and modified manually.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 include/hw/i386/ich9.h     |  2 +-
 hw/i386/acpi-build.c       |  4 ++--
 hw/i386/pc.c               | 18 +++++++++---------
 hw/i386/pc_piix.c          |  2 +-
 hw/i386/pc_q35.c           |  2 +-
 hw/i386/pc_sysfw.c         |  8 ++++----
 hw/i386/xen/xen-mapcache.c |  2 +-
 hw/intc/apic_common.c      |  2 +-
 hw/pci-host/gpex.c         |  2 +-
 hw/pci-host/piix.c         |  4 ++--
 hw/pci-host/q35.c          | 16 ++++++++--------
 11 files changed, 31 insertions(+), 31 deletions(-)

diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index 673d13d28f..87628dd867 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -22,7 +22,7 @@ I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
 
 void ich9_generate_smi(void);
 
-#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
+#define ICH9_CC_SIZE (16 * K_BYTE) /* Chipset configuration registers */
 
 #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
 #define ICH9_LPC_DEVICE(obj) \
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index deb440f286..9ccc6192b5 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2320,8 +2320,8 @@ build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
                  (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
 }
 
-#define HOLE_640K_START  (640 * 1024)
-#define HOLE_640K_END   (1024 * 1024)
+#define HOLE_640K_START  (640 * K_BYTE)
+#define HOLE_640K_END   (1024 * K_BYTE)
 
 static void
 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 55e69d66fe..94a1f3bc7b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -452,8 +452,8 @@ void pc_cmos_init(PCMachineState *pcms,
     rtc_set_memory(s, 0x15, val);
     rtc_set_memory(s, 0x16, val >> 8);
     /* extended memory (next 64MiB) */
-    if (pcms->below_4g_mem_size > 1024 * 1024) {
-        val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
+    if (pcms->below_4g_mem_size > 1 * M_BYTE) {
+        val = (pcms->below_4g_mem_size - 1 * M_BYTE) / 1024;
     } else {
         val = 0;
     }
@@ -464,8 +464,8 @@ void pc_cmos_init(PCMachineState *pcms,
     rtc_set_memory(s, 0x30, val);
     rtc_set_memory(s, 0x31, val >> 8);
     /* memory between 16MiB and 4GiB */
-    if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
-        val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
+    if (pcms->below_4g_mem_size > 16 * M_BYTE) {
+        val = (pcms->below_4g_mem_size - 16 * M_BYTE) / 65536;
     } else {
         val = 0;
     }
@@ -1390,11 +1390,11 @@ void pc_memory_init(PCMachineState *pcms,
         }
 
         pcms->hotplug_memory.base =
-            ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
+            ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, G_BYTE);
 
         if (pcmc->enforce_aligned_dimm) {
             /* size hotplug region assuming 1G page max alignment per slot */
-            hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
+            hotplug_mem_size += machine->ram_slots * G_BYTE;
         }
 
         if ((pcms->hotplug_memory.base + hotplug_mem_size) <
@@ -1436,7 +1436,7 @@ void pc_memory_init(PCMachineState *pcms,
         if (!pcmc->broken_reserved_end) {
             res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
         }
-        *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
+        *val = cpu_to_le64(ROUND_UP(res_mem_end, G_BYTE));
         fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
     }
 
@@ -1472,7 +1472,7 @@ uint64_t pc_pci_hole64_start(void)
         hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
     }
 
-    return ROUND_UP(hole64_start, 1ULL << 30);
+    return ROUND_UP(hole64_start, G_BYTE);
 }
 
 qemu_irq pc_allocate_cpu_irq(void)
@@ -2114,7 +2114,7 @@ static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
         return;
     }
 
-    if (value < (1ULL << 20)) {
+    if (value < 1 * M_BYTE) {
         warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
                     "BIOS may not work with less than 1MiB", value);
     }
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 456dc9e9f0..975dfc848e 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -131,7 +131,7 @@ static void pc_init1(MachineState *machine,
                 if (lowmem > 0xc0000000) {
                     lowmem = 0xc0000000;
                 }
-                if (lowmem & ((1ULL << 30) - 1)) {
+                if (lowmem & ((1 * G_BYTE) - 1)) {
                     warn_report("Large machine and max_ram_below_4g "
                                 "(%" PRIu64 ") not a multiple of 1G; "
                                 "possible bad performance.",
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index aba7541a82..79b84bc559 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -104,7 +104,7 @@ static void pc_q35_init(MachineState *machine)
     if (lowmem > pcms->max_ram_below_4g) {
         lowmem = pcms->max_ram_below_4g;
         if (machine->ram_size - lowmem > lowmem &&
-            lowmem & ((1ULL << 30) - 1)) {
+            lowmem & ((1 * G_BYTE) - 1)) {
             warn_report("There is possibly poor performance as the ram size "
                         " (0x%" PRIx64 ") is more then twice the size of"
                         " max-ram-below-4g (%"PRIu64") and"
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
index 4325575e7d..97488a832d 100644
--- a/hw/i386/pc_sysfw.c
+++ b/hw/i386/pc_sysfw.c
@@ -56,7 +56,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
     flash_size = memory_region_size(flash_mem);
 
     /* map the last 128KB of the BIOS in ISA space */
-    isa_bios_size = MIN(flash_size, 128 * 1024);
+    isa_bios_size = MIN(flash_size, 128 * K_BYTE);
     isa_bios = g_malloc(sizeof(*isa_bios));
     memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size,
                            &error_fatal);
@@ -83,7 +83,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
  * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
  * size.
  */
-#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8*1024*1024))
+#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8 * M_BYTE))
 
 /* This function maps flash drives from 4G downward, in order of their unit
  * numbers. The mapping starts at unit#0, with unit number increments of 1, and
@@ -209,8 +209,8 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
 
     /* map the last 128KB of the BIOS in ISA space */
     isa_bios_size = bios_size;
-    if (isa_bios_size > (128 * 1024)) {
-        isa_bios_size = 128 * 1024;
+    if (isa_bios_size > 128 * K_BYTE) {
+        isa_bios_size = 128 * K_BYTE;
     }
     isa_bios = g_malloc(sizeof(*isa_bios));
     memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
index efa35dc6e0..5f48fde799 100644
--- a/hw/i386/xen/xen-mapcache.c
+++ b/hw/i386/xen/xen-mapcache.c
@@ -47,7 +47,7 @@
  * From empirical tests I observed that qemu use 75MB more than the
  * max_mcache_size.
  */
-#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024)
+#define NON_MCACHE_MEMORY_SIZE (80 * M_BYTE)
 
 typedef struct MapCacheEntry {
     hwaddr paddr_index;
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index 78903ea909..3a6c297c52 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -319,7 +319,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
 
     /* Note: We need at least 1M to map the VAPIC option ROM */
     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
-        !hax_enabled() && ram_size >= 1024 * 1024) {
+        !hax_enabled() && ram_size >= 1 * M_BYTE) {
         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
     }
     s->vapic = vapic;
diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
index 2583b151a4..9cab9d0e7d 100644
--- a/hw/pci-host/gpex.c
+++ b/hw/pci-host/gpex.c
@@ -79,7 +79,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
 
     pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
     memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
-    memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
+    memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * K_BYTE);
 
     sysbus_init_mmio(sbd, &pex->mmio);
     sysbus_init_mmio(sbd, &s->io_mmio);
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 0e608347c1..7fc1822ec0 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -284,7 +284,7 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 
     pci_bus_get_w64_range(h->bus, &w64);
     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
-    hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
+    hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, G_BYTE);
     if (s->pci_hole64_fix && value < hole64_end) {
         value = hole64_end;
     }
@@ -430,7 +430,7 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 
     *piix3_devfn = piix3->dev.devfn;
 
-    ram_size = ram_size / 8 / 1024 / 1024;
+    ram_size /= 8 * M_BYTE;
     if (ram_size > 255) {
         ram_size = 255;
     }
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index a36a1195e4..a54b6736e5 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -144,7 +144,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
 
     pci_bus_get_w64_range(h->bus, &w64);
     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
-    hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
+    hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, G_BYTE);
     if (s->pci_hole64_fix && value < hole64_end) {
         value = hole64_end;
     }
@@ -310,15 +310,15 @@ static void mch_update_pciexbar(MCHPCIState *mch)
     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
-        length = 256 * 1024 * 1024;
+        length = 256 * M_BYTE;
         break;
     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
-        length = 128 * 1024 * 1024;
+        length = 128 * M_BYTE;
         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
         break;
     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
-        length = 64 * 1024 * 1024;
+        length = 64 * M_BYTE;
         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
         break;
     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
@@ -396,16 +396,16 @@ static void mch_update_smram(MCHPCIState *mch)
         switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
                 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
-            tseg_size = 1024 * 1024;
+            tseg_size = 1 * M_BYTE;
             break;
         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
-            tseg_size = 1024 * 1024 * 2;
+            tseg_size = 2 * M_BYTE;
             break;
         case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
-            tseg_size = 1024 * 1024 * 8;
+            tseg_size = 8 * M_BYTE;
             break;
         default:
-            tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
+            tseg_size = (uint32_t)mch->ext_tseg_mbytes * M_BYTE;
             break;
         }
     } else {
-- 
2.16.2


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[PATCH v2 22/30] hw/display: use the BYTE-based definitions

[Philippe Mathieu-Daudé]

It eases code review, unit is explicit.

Patch generated using:

  $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/

and modified manually.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
---
 hw/display/cirrus_vga.c |  9 ++++-----
 hw/display/g364fb.c     |  2 +-
 hw/display/qxl.c        | 26 +++++++++++---------------
 hw/display/vga-isa-mm.c |  4 ++--
 hw/display/vga.c        |  4 ++--
 hw/display/virtio-gpu.c |  3 +--
 hw/display/vmware_vga.c |  2 +-
 hw/display/xenfb.c      |  2 +-
 8 files changed, 23 insertions(+), 29 deletions(-)

diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
index 138ae961b9..e888056d75 100644
--- a/hw/display/cirrus_vga.c
+++ b/hw/display/cirrus_vga.c
@@ -2218,7 +2218,7 @@ static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
     uint32_t content;
     int y, y_min, y_max;
 
-    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
+    src = s->vga.vram_ptr + s->real_vram_size - 16 * K_BYTE;
     if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
         src += (s->vga.sr[0x13] & 0x3c) * 256;
         y_min = 64;
@@ -2347,7 +2347,7 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
         return;
     }
 
-    src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
+    src = s->vga.vram_ptr + s->real_vram_size - 16 * K_BYTE;
     if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
         src += (s->vga.sr[0x13] & 0x3c) * 256;
         src += (scr_y - s->vga.hw_cursor_y) * 16;
@@ -2995,8 +2995,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object *owner,
 
     /* I/O handler for LFB */
     memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
-                          "cirrus-linear-io", s->vga.vram_size_mb
-                                              * 1024 * 1024);
+                          "cirrus-linear-io", s->vga.vram_size_mb * M_BYTE);
     memory_region_set_flush_coalesced(&s->cirrus_linear_io);
 
     /* I/O handler for LFB */
@@ -3013,7 +3012,7 @@ static void cirrus_init_common(CirrusVGAState *s, Object *owner,
     memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
 
     s->real_vram_size =
-        (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
+        (s->device_id == CIRRUS_ID_CLGD5446) ? 4 * M_BYTE : 2 * M_BYTE;
 
     /* XXX: s->vga.vram_size must be a power of two */
     s->cirrus_addr_mask = s->real_vram_size - 1;
diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c
index 819f8be05d..009f07333b 100644
--- a/hw/display/g364fb.c
+++ b/hw/display/g364fb.c
@@ -510,7 +510,7 @@ static void g364fb_sysbus_reset(DeviceState *d)
 
 static Property g364fb_sysbus_properties[] = {
     DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size,
-    8 * 1024 * 1024),
+                       8 * M_BYTE),
     DEFINE_PROP_END_OF_LIST(),
 };
 
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index a71714ccb4..4863f894ad 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -2012,11 +2012,11 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
     if (qxl->vgamem_size_mb > 256) {
         qxl->vgamem_size_mb = 256;
     }
-    qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
+    qxl->vgamem_size = qxl->vgamem_size_mb * M_BYTE;
 
     /* vga ram (bar 0, total) */
     if (qxl->ram_size_mb != -1) {
-        qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
+        qxl->vga.vram_size = qxl->ram_size_mb * M_BYTE;
     }
     if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
         qxl->vga.vram_size = qxl->vgamem_size * 2;
@@ -2024,7 +2024,7 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
 
     /* vram32 (surfaces, 32bit, bar 1) */
     if (qxl->vram32_size_mb != -1) {
-        qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
+        qxl->vram32_size = qxl->vram32_size_mb * M_BYTE;
     }
     if (qxl->vram32_size < 4096) {
         qxl->vram32_size = 4096;
@@ -2032,7 +2032,7 @@ static void qxl_init_ramsize(PCIQXLDevice *qxl)
 
     /* vram (surfaces, 64bit, bar 4+5) */
     if (qxl->vram_size_mb != -1) {
-        qxl->vram_size = (uint64_t)qxl->vram_size_mb * 1024 * 1024;
+        qxl->vram_size = (uint64_t)qxl->vram_size_mb * M_BYTE;
     }
     if (qxl->vram_size < qxl->vram32_size) {
         qxl->vram_size = qxl->vram32_size;
@@ -2134,13 +2134,10 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp)
     }
 
     /* print pci bar details */
-    dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
-           qxl->id == 0 ? "pri" : "sec",
-           qxl->vga.vram_size / (1024*1024));
-    dprint(qxl, 1, "vram/32: %" PRIx64 "d MB [region 1]\n",
-           qxl->vram32_size / (1024*1024));
-    dprint(qxl, 1, "vram/64: %" PRIx64 "d MB %s\n",
-           qxl->vram_size / (1024*1024),
+    dprint(qxl, 1, "ram/%s: %llu MB [region 0]\n",
+           qxl->id == 0 ? "pri" : "sec", qxl->vga.vram_size / M_BYTE);
+    dprint(qxl, 1, "vram/32: %llu MB [region 1]\n", qxl->vram32_size / M_BYTE);
+    dprint(qxl, 1, "vram/64: %llu MB %s\n", qxl->vram_size / M_BYTE,
            qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
 
     qxl->ssd.qxl.base.sif = &qxl_interface.base;
@@ -2167,7 +2164,7 @@ static void qxl_realize_primary(PCIDevice *dev, Error **errp)
     qxl->id = 0;
     qxl_init_ramsize(qxl);
     vga->vbe_size = qxl->vgamem_size;
-    vga->vram_size_mb = qxl->vga.vram_size >> 20;
+    vga->vram_size_mb = qxl->vga.vram_size / M_BYTE;
     vga_common_init(vga, OBJECT(dev), true);
     vga_init(vga, OBJECT(dev),
              pci_address_space(dev), pci_address_space_io(dev), false);
@@ -2392,9 +2389,8 @@ static VMStateDescription qxl_vmstate = {
 
 static Property qxl_properties[] = {
         DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
-                           64 * 1024 * 1024),
-        DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size,
-                           64 * 1024 * 1024),
+                           64 * M_BYTE),
+        DEFINE_PROP_UINT64("vram_size", PCIQXLDevice, vram32_size, 64 * M_BYTE),
         DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
                            QXL_DEFAULT_REVISION),
         DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
diff --git a/hw/display/vga-isa-mm.c b/hw/display/vga-isa-mm.c
index e887b45651..79a5950144 100644
--- a/hw/display/vga-isa-mm.c
+++ b/hw/display/vga-isa-mm.c
@@ -27,7 +27,7 @@
 #include "vga_int.h"
 #include "ui/pixel_ops.h"
 
-#define VGA_RAM_SIZE (8192 * 1024)
+#define VGA_RAM_SIZE (8 * M_BYTE)
 
 typedef struct ISAVGAMMState {
     VGACommonState vga;
@@ -130,7 +130,7 @@ int isa_vga_mm_init(hwaddr vram_base,
 
     s = g_malloc0(sizeof(*s));
 
-    s->vga.vram_size_mb = VGA_RAM_SIZE >> 20;
+    s->vga.vram_size_mb = VGA_RAM_SIZE / M_BYTE;
     vga_common_init(&s->vga, NULL, true);
     vga_mm_init(s, vram_base, ctrl_base, it_shift, address_space);
 
diff --git a/hw/display/vga.c b/hw/display/vga.c
index 28f298b342..8f4527b3a0 100644
--- a/hw/display/vga.c
+++ b/hw/display/vga.c
@@ -721,7 +721,7 @@ uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
             val = s->vbe_regs[s->vbe_index];
         }
     } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
-        val = s->vbe_size / (64 * 1024);
+        val = s->vbe_size / (64 * K_BYTE);
     } else {
         val = 0;
     }
@@ -2175,7 +2175,7 @@ void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
 
     s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512);
     s->vram_size_mb = pow2ceil(s->vram_size_mb);
-    s->vram_size = s->vram_size_mb << 20;
+    s->vram_size = s->vram_size_mb * M_BYTE;
 
     if (!s->vbe_size) {
         s->vbe_size = s->vram_size;
diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c
index 2dd3c3481a..72e3678da3 100644
--- a/hw/display/virtio-gpu.c
+++ b/hw/display/virtio-gpu.c
@@ -1314,8 +1314,7 @@ static const VMStateDescription vmstate_virtio_gpu = {
 
 static Property virtio_gpu_properties[] = {
     DEFINE_PROP_UINT32("max_outputs", VirtIOGPU, conf.max_outputs, 1),
-    DEFINE_PROP_SIZE("max_hostmem", VirtIOGPU, conf.max_hostmem,
-                     256 * 1024 * 1024),
+    DEFINE_PROP_SIZE("max_hostmem", VirtIOGPU, conf.max_hostmem, 256 * M_BYTE),
 #ifdef CONFIG_VIRGL
     DEFINE_PROP_BIT("virgl", VirtIOGPU, conf.flags,
                     VIRTIO_GPU_FLAG_VIRGL_ENABLED, true),
diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c
index bd3e8b3586..8609f9c0bc 100644
--- a/hw/display/vmware_vga.c
+++ b/hw/display/vmware_vga.c
@@ -565,7 +565,7 @@ static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
         s->fifo_next >= SVGA_FIFO_SIZE) {
         return 0;
     }
-    if (s->fifo_max < s->fifo_min + 10 * 1024) {
+    if (s->fifo_max < s->fifo_min + 10 * K_BYTE) {
         return 0;
     }
 
diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c
index f5afcc0358..1ae660519a 100644
--- a/hw/display/xenfb.c
+++ b/hw/display/xenfb.c
@@ -889,7 +889,7 @@ static int fb_initialise(struct XenDevice *xendev)
 	return rc;
 
     fb_page = fb->c.page;
-    rc = xenfb_configure_fb(fb, videoram * 1024 * 1024U,
+    rc = xenfb_configure_fb(fb, videoram * M_BYTE,
 			    fb_page->width, fb_page->height, fb_page->depth,
 			    fb_page->mem_length, 0, fb_page->line_length);
     if (rc != 0)
-- 
2.16.2


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[PATCH v2 30/30] xen: use the BYTE-based definitions

[Philippe Mathieu-Daudé]

It eases code review, unit is explicit.

Patch generated using:

  $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/

and modified manually.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alan Robinson <Alan.Robinson@ts.fujitsu.com>
---
 hw/block/xen_disk.c        |  4 ++--
 hw/xenpv/xen_domainbuild.c | 10 +++++-----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/block/xen_disk.c b/hw/block/xen_disk.c
index f74fcd42d1..557005b5e5 100644
--- a/hw/block/xen_disk.c
+++ b/hw/block/xen_disk.c
@@ -1153,9 +1153,9 @@ static int blk_connect(struct XenDevice *xendev)
     }
 
     xen_pv_printf(xendev, 1, "type \"%s\", fileproto \"%s\", filename \"%s\","
-                  " size %" PRId64 " (%" PRId64 " MB)\n",
+                  " size %" PRId64 " (%llu MB)\n",
                   blkdev->type, blkdev->fileproto, blkdev->filename,
-                  blkdev->file_size, blkdev->file_size >> 20);
+                  blkdev->file_size, blkdev->file_size / M_BYTE);
 
     /* Fill in number of sector size and number of sectors */
     xenstore_write_be_int(&blkdev->xendev, "sector-size", blkdev->file_blk);
diff --git a/hw/xenpv/xen_domainbuild.c b/hw/xenpv/xen_domainbuild.c
index 027f76fad1..7c8bde20cd 100644
--- a/hw/xenpv/xen_domainbuild.c
+++ b/hw/xenpv/xen_domainbuild.c
@@ -75,9 +75,9 @@ int xenstore_domain_init1(const char *kernel, const char *ramdisk,
     xenstore_write_str(dom, "vm",     vm);
 
     /* memory */
-    xenstore_write_int(dom, "memory/target", ram_size >> 10);  // kB
-    xenstore_write_int(vm, "memory",         ram_size >> 20);  // MB
-    xenstore_write_int(vm, "maxmem",         ram_size >> 20);  // MB
+    xenstore_write_int(dom, "memory/target", ram_size / K_BYTE);
+    xenstore_write_int(vm, "memory",         ram_size / M_BYTE);
+    xenstore_write_int(vm, "maxmem",         ram_size / M_BYTE);
 
     /* cpus */
     for (i = 0; i < smp_cpus; i++) {
@@ -260,7 +260,7 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
     }
 #endif
 
-    rc = xc_domain_setmaxmem(xen_xc, xen_domid, ram_size >> 10);
+    rc = xc_domain_setmaxmem(xen_xc, xen_domid, ram_size / K_BYTE);
     if (rc < 0) {
         fprintf(stderr, "xen: xc_domain_setmaxmem() failed\n");
         goto err;
@@ -269,7 +269,7 @@ int xen_domain_build_pv(const char *kernel, const char *ramdisk,
     xenstore_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0);
     console_port = xc_evtchn_alloc_unbound(xen_xc, xen_domid, 0);
 
-    rc = xc_linux_build(xen_xc, xen_domid, ram_size >> 20,
+    rc = xc_linux_build(xen_xc, xen_domid, ram_size / M_BYTE,
                         kernel, ramdisk, cmdline,
                         0, flags,
                         xenstore_port, &xenstore_mfn,
-- 
2.16.2


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Re: [PATCH v2 08/30] hw/i386: use the BYTE-based definitions

[Anthony PERARD]

On Mon, Mar 05, 2018 at 08:27:10AM -0300, Philippe Mathieu-Daudé wrote:
> It eases code review, unit is explicit.
> 
> Patch generated using:
> 
>   $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
> 
> and modified manually.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/i386/xen/xen-mapcache.c |  2 +-
> 
> diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
> index efa35dc6e0..5f48fde799 100644
> --- a/hw/i386/xen/xen-mapcache.c
> +++ b/hw/i386/xen/xen-mapcache.c
> @@ -47,7 +47,7 @@
>   * From empirical tests I observed that qemu use 75MB more than the
>   * max_mcache_size.
>   */
> -#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024)
> +#define NON_MCACHE_MEMORY_SIZE (80 * M_BYTE)
>  
>  typedef struct MapCacheEntry {
>      hwaddr paddr_index;

Acked-by: Anthony PERARD <anthony.perard@citrix.com>

-- 
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Re: [PATCH v2 22/30] hw/display: use the BYTE-based definitions

[Anthony PERARD]

On Mon, Mar 05, 2018 at 08:27:24AM -0300, Philippe Mathieu-Daudé wrote:
> It eases code review, unit is explicit.
> 
> Patch generated using:
> 
>   $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
> 
> and modified manually.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
>  hw/display/xenfb.c      |  2 +-
> diff --git a/hw/display/xenfb.c b/hw/display/xenfb.c
> index f5afcc0358..1ae660519a 100644
> --- a/hw/display/xenfb.c
> +++ b/hw/display/xenfb.c
> @@ -889,7 +889,7 @@ static int fb_initialise(struct XenDevice *xendev)
>  	return rc;
>  
>      fb_page = fb->c.page;
> -    rc = xenfb_configure_fb(fb, videoram * 1024 * 1024U,
> +    rc = xenfb_configure_fb(fb, videoram * M_BYTE,
>  			    fb_page->width, fb_page->height, fb_page->depth,
>  			    fb_page->mem_length, 0, fb_page->line_length);
>      if (rc != 0)

Acked-by: Anthony PERARD <anthony.perard@citrix.com>

Thanks,

-- 
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Re: [PATCH v2 30/30] xen: use the BYTE-based definitions

[Anthony PERARD]

On Mon, Mar 05, 2018 at 08:27:32AM -0300, Philippe Mathieu-Daudé wrote:
> It eases code review, unit is explicit.
> 
> Patch generated using:
> 
>   $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
> 
> and modified manually.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Alan Robinson <Alan.Robinson@ts.fujitsu.com>
> ---
>  hw/block/xen_disk.c        |  4 ++--
>  hw/xenpv/xen_domainbuild.c | 10 +++++-----
>  2 files changed, 7 insertions(+), 7 deletions(-)
> 

Acked-by: Anthony PERARD <anthony.perard@citrix.com>

Thanks,

-- 
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Re: [Qemu-devel] [PATCH v2 08/30] hw/i386: use the BYTE-based definitions

[Igor Mammedov]

On Mon,  5 Mar 2018 08:27:10 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:

> It eases code review, unit is explicit.
> 
> Patch generated using:
> 
>   $ git grep -E '(1024|2048|4096|8192|(<<|>>).?(10|20|30))' hw/ include/hw/
> 
> and modified manually.
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
My apologies,
compilation errors were my mistake of not applying 1-2/30 patches first.

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

> ---
>  include/hw/i386/ich9.h     |  2 +-
>  hw/i386/acpi-build.c       |  4 ++--
>  hw/i386/pc.c               | 18 +++++++++---------
>  hw/i386/pc_piix.c          |  2 +-
>  hw/i386/pc_q35.c           |  2 +-
>  hw/i386/pc_sysfw.c         |  8 ++++----
>  hw/i386/xen/xen-mapcache.c |  2 +-
>  hw/intc/apic_common.c      |  2 +-
>  hw/pci-host/gpex.c         |  2 +-
>  hw/pci-host/piix.c         |  4 ++--
>  hw/pci-host/q35.c          | 16 ++++++++--------
>  11 files changed, 31 insertions(+), 31 deletions(-)
> 
> diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> index 673d13d28f..87628dd867 100644
> --- a/include/hw/i386/ich9.h
> +++ b/include/hw/i386/ich9.h
> @@ -22,7 +22,7 @@ I2CBus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
>  
>  void ich9_generate_smi(void);
>  
> -#define ICH9_CC_SIZE (16 * 1024) /* 16KB. Chipset configuration registers */
> +#define ICH9_CC_SIZE (16 * K_BYTE) /* Chipset configuration registers */
>  
>  #define TYPE_ICH9_LPC_DEVICE "ICH9-LPC"
>  #define ICH9_LPC_DEVICE(obj) \
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index deb440f286..9ccc6192b5 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -2320,8 +2320,8 @@ build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
>                   (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
>  }
>  
> -#define HOLE_640K_START  (640 * 1024)
> -#define HOLE_640K_END   (1024 * 1024)
> +#define HOLE_640K_START  (640 * K_BYTE)
> +#define HOLE_640K_END   (1024 * K_BYTE)
>  
>  static void
>  build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 55e69d66fe..94a1f3bc7b 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -452,8 +452,8 @@ void pc_cmos_init(PCMachineState *pcms,
>      rtc_set_memory(s, 0x15, val);
>      rtc_set_memory(s, 0x16, val >> 8);
>      /* extended memory (next 64MiB) */
> -    if (pcms->below_4g_mem_size > 1024 * 1024) {
> -        val = (pcms->below_4g_mem_size - 1024 * 1024) / 1024;
> +    if (pcms->below_4g_mem_size > 1 * M_BYTE) {
> +        val = (pcms->below_4g_mem_size - 1 * M_BYTE) / 1024;
>      } else {
>          val = 0;
>      }
> @@ -464,8 +464,8 @@ void pc_cmos_init(PCMachineState *pcms,
>      rtc_set_memory(s, 0x30, val);
>      rtc_set_memory(s, 0x31, val >> 8);
>      /* memory between 16MiB and 4GiB */
> -    if (pcms->below_4g_mem_size > 16 * 1024 * 1024) {
> -        val = (pcms->below_4g_mem_size - 16 * 1024 * 1024) / 65536;
> +    if (pcms->below_4g_mem_size > 16 * M_BYTE) {
> +        val = (pcms->below_4g_mem_size - 16 * M_BYTE) / 65536;
>      } else {
>          val = 0;
>      }
> @@ -1390,11 +1390,11 @@ void pc_memory_init(PCMachineState *pcms,
>          }
>  
>          pcms->hotplug_memory.base =
> -            ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, 1ULL << 30);
> +            ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, G_BYTE);
>  
>          if (pcmc->enforce_aligned_dimm) {
>              /* size hotplug region assuming 1G page max alignment per slot */
> -            hotplug_mem_size += (1ULL << 30) * machine->ram_slots;
> +            hotplug_mem_size += machine->ram_slots * G_BYTE;
>          }
>  
>          if ((pcms->hotplug_memory.base + hotplug_mem_size) <
> @@ -1436,7 +1436,7 @@ void pc_memory_init(PCMachineState *pcms,
>          if (!pcmc->broken_reserved_end) {
>              res_mem_end += memory_region_size(&pcms->hotplug_memory.mr);
>          }
> -        *val = cpu_to_le64(ROUND_UP(res_mem_end, 0x1ULL << 30));
> +        *val = cpu_to_le64(ROUND_UP(res_mem_end, G_BYTE));
>          fw_cfg_add_file(fw_cfg, "etc/reserved-memory-end", val, sizeof(*val));
>      }
>  
> @@ -1472,7 +1472,7 @@ uint64_t pc_pci_hole64_start(void)
>          hole64_start = 0x100000000ULL + pcms->above_4g_mem_size;
>      }
>  
> -    return ROUND_UP(hole64_start, 1ULL << 30);
> +    return ROUND_UP(hole64_start, G_BYTE);
>  }
>  
>  qemu_irq pc_allocate_cpu_irq(void)
> @@ -2114,7 +2114,7 @@ static void pc_machine_set_max_ram_below_4g(Object *obj, Visitor *v,
>          return;
>      }
>  
> -    if (value < (1ULL << 20)) {
> +    if (value < 1 * M_BYTE) {
>          warn_report("Only %" PRIu64 " bytes of RAM below the 4GiB boundary,"
>                      "BIOS may not work with less than 1MiB", value);
>      }
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 456dc9e9f0..975dfc848e 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -131,7 +131,7 @@ static void pc_init1(MachineState *machine,
>                  if (lowmem > 0xc0000000) {
>                      lowmem = 0xc0000000;
>                  }
> -                if (lowmem & ((1ULL << 30) - 1)) {
> +                if (lowmem & ((1 * G_BYTE) - 1)) {
>                      warn_report("Large machine and max_ram_below_4g "
>                                  "(%" PRIu64 ") not a multiple of 1G; "
>                                  "possible bad performance.",
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index aba7541a82..79b84bc559 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -104,7 +104,7 @@ static void pc_q35_init(MachineState *machine)
>      if (lowmem > pcms->max_ram_below_4g) {
>          lowmem = pcms->max_ram_below_4g;
>          if (machine->ram_size - lowmem > lowmem &&
> -            lowmem & ((1ULL << 30) - 1)) {
> +            lowmem & ((1 * G_BYTE) - 1)) {
>              warn_report("There is possibly poor performance as the ram size "
>                          " (0x%" PRIx64 ") is more then twice the size of"
>                          " max-ram-below-4g (%"PRIu64") and"
> diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
> index 4325575e7d..97488a832d 100644
> --- a/hw/i386/pc_sysfw.c
> +++ b/hw/i386/pc_sysfw.c
> @@ -56,7 +56,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
>      flash_size = memory_region_size(flash_mem);
>  
>      /* map the last 128KB of the BIOS in ISA space */
> -    isa_bios_size = MIN(flash_size, 128 * 1024);
> +    isa_bios_size = MIN(flash_size, 128 * K_BYTE);
>      isa_bios = g_malloc(sizeof(*isa_bios));
>      memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size,
>                             &error_fatal);
> @@ -83,7 +83,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory,
>   * only 18MB-4KB below 4G. For now, restrict the cumulative mapping to 8MB in
>   * size.
>   */
> -#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8*1024*1024))
> +#define FLASH_MAP_BASE_MIN ((hwaddr)(0x100000000ULL - 8 * M_BYTE))
>  
>  /* This function maps flash drives from 4G downward, in order of their unit
>   * numbers. The mapping starts at unit#0, with unit number increments of 1, and
> @@ -209,8 +209,8 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw)
>  
>      /* map the last 128KB of the BIOS in ISA space */
>      isa_bios_size = bios_size;
> -    if (isa_bios_size > (128 * 1024)) {
> -        isa_bios_size = 128 * 1024;
> +    if (isa_bios_size > 128 * K_BYTE) {
> +        isa_bios_size = 128 * K_BYTE;
>      }
>      isa_bios = g_malloc(sizeof(*isa_bios));
>      memory_region_init_alias(isa_bios, NULL, "isa-bios", bios,
> diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c
> index efa35dc6e0..5f48fde799 100644
> --- a/hw/i386/xen/xen-mapcache.c
> +++ b/hw/i386/xen/xen-mapcache.c
> @@ -47,7 +47,7 @@
>   * From empirical tests I observed that qemu use 75MB more than the
>   * max_mcache_size.
>   */
> -#define NON_MCACHE_MEMORY_SIZE (80 * 1024 * 1024)
> +#define NON_MCACHE_MEMORY_SIZE (80 * M_BYTE)
>  
>  typedef struct MapCacheEntry {
>      hwaddr paddr_index;
> diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
> index 78903ea909..3a6c297c52 100644
> --- a/hw/intc/apic_common.c
> +++ b/hw/intc/apic_common.c
> @@ -319,7 +319,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp)
>  
>      /* Note: We need at least 1M to map the VAPIC option ROM */
>      if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
> -        !hax_enabled() && ram_size >= 1024 * 1024) {
> +        !hax_enabled() && ram_size >= 1 * M_BYTE) {
>          vapic = sysbus_create_simple("kvmvapic", -1, NULL);
>      }
>      s->vapic = vapic;
> diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c
> index 2583b151a4..9cab9d0e7d 100644
> --- a/hw/pci-host/gpex.c
> +++ b/hw/pci-host/gpex.c
> @@ -79,7 +79,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp)
>  
>      pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
>      memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
> -    memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
> +    memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * K_BYTE);
>  
>      sysbus_init_mmio(sbd, &pex->mmio);
>      sysbus_init_mmio(sbd, &s->io_mmio);
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 0e608347c1..7fc1822ec0 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -284,7 +284,7 @@ static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
>  
>      pci_bus_get_w64_range(h->bus, &w64);
>      value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
> -    hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
> +    hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, G_BYTE);
>      if (s->pci_hole64_fix && value < hole64_end) {
>          value = hole64_end;
>      }
> @@ -430,7 +430,7 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
>  
>      *piix3_devfn = piix3->dev.devfn;
>  
> -    ram_size = ram_size / 8 / 1024 / 1024;
> +    ram_size /= 8 * M_BYTE;
>      if (ram_size > 255) {
>          ram_size = 255;
>      }
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index a36a1195e4..a54b6736e5 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -144,7 +144,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
>  
>      pci_bus_get_w64_range(h->bus, &w64);
>      value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
> -    hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
> +    hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, G_BYTE);
>      if (s->pci_hole64_fix && value < hole64_end) {
>          value = hole64_end;
>      }
> @@ -310,15 +310,15 @@ static void mch_update_pciexbar(MCHPCIState *mch)
>      addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
>      switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
>      case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
> -        length = 256 * 1024 * 1024;
> +        length = 256 * M_BYTE;
>          break;
>      case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
> -        length = 128 * 1024 * 1024;
> +        length = 128 * M_BYTE;
>          addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
>              MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
>          break;
>      case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
> -        length = 64 * 1024 * 1024;
> +        length = 64 * M_BYTE;
>          addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
>          break;
>      case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
> @@ -396,16 +396,16 @@ static void mch_update_smram(MCHPCIState *mch)
>          switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
>                  MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
>          case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
> -            tseg_size = 1024 * 1024;
> +            tseg_size = 1 * M_BYTE;
>              break;
>          case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
> -            tseg_size = 1024 * 1024 * 2;
> +            tseg_size = 2 * M_BYTE;
>              break;
>          case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
> -            tseg_size = 1024 * 1024 * 8;
> +            tseg_size = 8 * M_BYTE;
>              break;
>          default:
> -            tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
> +            tseg_size = (uint32_t)mch->ext_tseg_mbytes * M_BYTE;
>              break;
>          }
>      } else {


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