Re: [PATCH v10 01/11] vpci: introduce basic handlers to trap accesses to the PCI config space

From: Wei Liu <wei.liu2@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
	Wei Liu <wei.liu2@citrix.com>,
	George Dunlap <George.Dunlap@eu.citrix.com>,
	AndrewCooper <andrew.cooper3@citrix.com>,
	Ian Jackson <ian.jackson@eu.citrix.com>, TimDeegan <tim@xen.org>,
	Julien Grall <julien.grall@arm.com>,
	Paul Durrant <paul.durrant@citrix.com>,
	xen-devel@lists.xenproject.org,
	Boris Ostrovsky <boris.ostrovsky@oracle.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH v10 01/11] vpci: introduce basic handlers to trap accesses to the PCI config space
Date: Wed, 21 Mar 2018 16:01:41 +0000	[thread overview]
Message-ID: <20180321160141.keh2gtzy2ayfsvbh@citrix.com> (raw)
In-Reply-To: <5AB0FA2102000078001B3E3A@prv-mh.provo.novell.com>

On Tue, Mar 20, 2018 at 05:10:09AM -0600, Jan Beulich wrote:
> >>> On 16.03.18 at 14:29, <roger.pau@citrix.com> wrote:
> > This functionality is going to reside in vpci.c (and the corresponding
> > vpci.h header), and should be arch-agnostic. The handlers introduced
> > in this patch setup the basic functionality required in order to trap
> > accesses to the PCI config space, and allow decoding the address and
> > finding the corresponding handler that should handle the access
> > (although no handlers are implemented).
> > 
> > Note that the traps to the PCI IO ports registers (0xcf8/0xcfc) are
> > setup inside of a x86 HVM file, since that's not shared with other
> > arches.
> > 
> > A new XEN_X86_EMU_VPCI x86 domain flag is added in order to signal Xen
> > whether a domain should use the newly introduced vPCI handlers, this
> > is only enabled for PVH Dom0 at the moment.
> > 
> > A very simple user-space test is also provided, so that the basic
> > functionality of the vPCI traps can be asserted. This has been proven
> > quite helpful during development, since the logic to handle partial
> > accesses or accesses that expand across multiple registers is not
> > trivial.
> > 
> > The handlers for the registers are added to a linked list that's keep
> > sorted at all times. Both the read and write handlers support accesses
> > that expand across multiple emulated registers and contain gaps not
> > emulated.
> > 
> > Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
> > Reviewed-by: Jan Beulich <jbeulich@suse.com>
> > [IO parts]
> > Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
> 
> Stefano, Julien,
> 
> any chance of getting an ack for the smallish ARM side change
> here (assuming your earlier concerns have been addressed)?
> 
> Ian, Wei,
> 
> along those lines (iirc there were no prior concerns) for the tiny
> libxl part? (I think the new test code doesn't strictly belong under
> tools/ maintainership, just like the x86_emulator one doesn't.)

Here you go:

Acked-by: Wei Liu <wei.liu2@citrix.com>

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