Re: [PATCH 01/10] x86/spec_ctrl: Read MSR_ARCH_CAPABILITIES only once

[Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>]

On Fri, May 11, 2018 at 11:38:05AM +0100, Andrew Cooper wrote:
> Make it available from the beginning of init_speculation_mitigations(), and
> pass it into appropriate functions.  Fix an RSBA typo while moving the
> affected comment.
> 
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

Thank you!
> ---
> CC: Jan Beulich <JBeulich@suse.com>
> CC: Wei Liu <wei.liu2@citrix.com>
> CC: Roger Pau Monné <roger.pau@citrix.com>
> CC: Juergen Gross <jgross@suse.com>
> ---
>  xen/arch/x86/spec_ctrl.c | 34 ++++++++++++++--------------------
>  1 file changed, 14 insertions(+), 20 deletions(-)
> 
> diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
> index 037e84d..4ab0f50 100644
> --- a/xen/arch/x86/spec_ctrl.c
> +++ b/xen/arch/x86/spec_ctrl.c
> @@ -97,18 +97,15 @@ static int __init parse_bti(const char *s)
>  }
>  custom_param("bti", parse_bti);
>  
> -static void __init print_details(enum ind_thunk thunk)
> +static void __init print_details(enum ind_thunk thunk, uint64_t caps)
>  {
>      unsigned int _7d0 = 0, e8b = 0, tmp;
> -    uint64_t caps = 0;
>  
>      /* Collect diagnostics about available mitigations. */
>      if ( boot_cpu_data.cpuid_level >= 7 )
>          cpuid_count(7, 0, &tmp, &tmp, &tmp, &_7d0);
>      if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
>          cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
> -    if ( _7d0 & cpufeat_mask(X86_FEATURE_ARCH_CAPS) )
> -        rdmsrl(MSR_ARCH_CAPABILITIES, caps);
>  
>      printk(XENLOG_DEBUG "Speculative mitigation facilities:\n");
>  
> @@ -142,7 +139,7 @@ static void __init print_details(enum ind_thunk thunk)
>  }
>  
>  /* Calculate whether Retpoline is known-safe on this CPU. */
> -static bool __init retpoline_safe(void)
> +static bool __init retpoline_safe(uint64_t caps)
>  {
>      unsigned int ucode_rev = this_cpu(ucode_cpu_info).cpu_sig.rev;
>  
> @@ -153,19 +150,12 @@ static bool __init retpoline_safe(void)
>           boot_cpu_data.x86 != 6 )
>          return false;
>  
> -    if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
> -    {
> -        uint64_t caps;
> -
> -        rdmsrl(MSR_ARCH_CAPABILITIES, caps);
> -
> -        /*
> -         * RBSA may be set by a hypervisor to indicate that we may move to a
> -         * processor which isn't retpoline-safe.
> -         */
> -        if ( caps & ARCH_CAPS_RSBA )
> -            return false;
> -    }
> +    /*
> +     * RSBA may be set by a hypervisor to indicate that we may move to a
> +     * processor which isn't retpoline-safe.
> +     */
> +    if ( caps & ARCH_CAPS_RSBA )
> +        return false;
>  
>      switch ( boot_cpu_data.x86_model )
>      {
> @@ -299,6 +289,10 @@ void __init init_speculation_mitigations(void)
>  {
>      enum ind_thunk thunk = THUNK_DEFAULT;
>      bool ibrs = false;
> +    uint64_t caps = 0;
> +
> +    if ( boot_cpu_has(X86_FEATURE_ARCH_CAPS) )
> +        rdmsrl(MSR_ARCH_CAPABILITIES, caps);
>  
>      /*
>       * Has the user specified any custom BTI mitigations?  If so, follow their
> @@ -327,7 +321,7 @@ void __init init_speculation_mitigations(void)
>               * On Intel hardware, we'd like to use retpoline in preference to
>               * IBRS, but only if it is safe on this hardware.
>               */
> -            else if ( retpoline_safe() )
> +            else if ( retpoline_safe(caps) )
>                  thunk = THUNK_RETPOLINE;
>              else if ( boot_cpu_has(X86_FEATURE_IBRSB) )
>                  ibrs = true;
> @@ -418,7 +412,7 @@ void __init init_speculation_mitigations(void)
>      else
>          setup_clear_cpu_cap(X86_FEATURE_NO_XPTI);
>  
> -    print_details(thunk);
> +    print_details(thunk, caps);
>  }
>  
>  static void __init __maybe_unused build_assertions(void)
> -- 
> 2.1.4
> 
> 
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