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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: xen-devel <xen-devel@lists.xenproject.org>,
	Brian Woods <brian.woods@amd.com>,
	Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH v4 5/5] amd/iommu: skip bridge devices when updating IOMMU page tables
Date: Thu, 15 Nov 2018 16:48:08 +0100	[thread overview]
Message-ID: <20181115154808.s5natbctutnd7ztd@mac> (raw)
In-Reply-To: <5BED935B02000078001FC7A4@prv1-mh.provo.novell.com>

On Thu, Nov 15, 2018 at 08:40:11AM -0700, Jan Beulich wrote:
> >>> On 14.11.18 at 12:57, <roger.pau@citrix.com> wrote:
> > Bridges are not behind an IOMMU, and are already special cased and
> > silently skipped in amd_iommu_add_device. Apply the same special
> > casing when updating page tables.
> 
> But bridges also don't issue I/O on their own if I'm not mistaken. So
> what I'm missing here is a word on the benefit of this change. I also
> question the "silently" in your wording, seeing the AMD_IOMMU_DEBUG()
> there.

I see, by silently I meant without throwing an error, but I think just
using 'skipped' would be clearer.

The benefit is that update_paging_mode doesn't return an error when it
finds a bridge attached to Dom0, which would cause the caller of
update_paging_mode (amd_iommu_{un}map_page) to crash the domain.

Ie: without this change a PVH Dom0 running on AMD hardware crashes
when the IOMMU page table is expanded.

> The code change itself looks fine to me, albeit personally I'd prefer
> if it fully matched the other conditional (i.e. if you flipped the
> operands of && ). Of course the special casing of the hardware
> domain here is somewhat odd anyway.

Do you mean because bridges would only be ever assigned to the
hardware domain?

Thanks, Roger.

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  reply	other threads:[~2018-11-15 15:48 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-14 11:57 [PATCH v4 0/5] x86/pvh: fix fixes for PVH Dom0 Roger Pau Monne
2018-11-14 11:57 ` [PATCH v4 1/5] vpci: fix updating the command register Roger Pau Monne
2018-11-16 12:00   ` Jan Beulich
2018-11-16 14:32     ` Roger Pau Monné
2018-11-19  8:26       ` Jan Beulich
2018-11-19 11:09         ` Roger Pau Monné
2018-11-19 11:31           ` Jan Beulich
2018-11-14 11:57 ` [PATCH v4 2/5] vpci: fix deferral of long operations Roger Pau Monne
2018-11-14 12:08   ` Paul Durrant
2018-11-16 12:11   ` Jan Beulich
2018-11-16 14:57     ` Roger Pau Monné
2018-11-19  8:27       ` Jan Beulich
2018-11-14 11:57 ` [PATCH v4 3/5] vpci/msix: carve p2m hole for MSIX MMIO regions Roger Pau Monne
2018-11-19 14:56   ` Jan Beulich
2018-11-20 14:35     ` Roger Pau Monné
2018-11-14 11:57 ` [PATCH v4 4/5] amd/iommu: assign iommu devices to Xen Roger Pau Monne
2018-11-14 12:33   ` Andrew Cooper
2018-11-14 13:53     ` Jan Beulich
2018-11-14 16:09     ` Roger Pau Monné
2018-11-15 15:34   ` Jan Beulich
2018-11-15 16:00     ` Roger Pau Monné
2018-11-14 11:57 ` [PATCH v4 5/5] amd/iommu: skip bridge devices when updating IOMMU page tables Roger Pau Monne
2018-11-15 15:40   ` Jan Beulich
2018-11-15 15:48     ` Roger Pau Monné [this message]
2018-11-15 16:13       ` Jan Beulich

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