From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
Wei Liu <wei.liu2@citrix.com>,
Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
George Dunlap <George.Dunlap@eu.citrix.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Ian Jackson <Ian.Jackson@eu.citrix.com>, Tim Deegan <tim@xen.org>,
Julien Grall <julien.grall@arm.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v4 1/5] vpci: fix updating the command register
Date: Fri, 16 Nov 2018 15:32:45 +0100 [thread overview]
Message-ID: <20181116143245.vpk3vgpbcqujvofb@mac> (raw)
In-Reply-To: <5BEEB15D02000078001FCB9A@prv1-mh.provo.novell.com>
On Fri, Nov 16, 2018 at 05:00:29AM -0700, Jan Beulich wrote:
> >>> On 14.11.18 at 12:57, <roger.pau@citrix.com> wrote:
> > @@ -413,7 +412,7 @@ static void rom_write(const struct pci_dev *pdev, unsigned int reg,
> > header->rom_enabled = new_enabled;
> > pci_conf_write32(pdev->seg, pdev->bus, slot, func, reg, val);
> > }
> > - else if ( modify_bars(pdev, new_enabled, true) )
> > + else if ( modify_bars(pdev, new_enabled ? PCI_COMMAND_MEMORY : 0, true) )
>
> Do you really mean to clear all other defined bits of the command
> register here?
This is a ROM BAR write, not a command register write. rom_write
passes PCI_COMMAND_MEMORY merely to signal this is a mapping
operation, but the value would never be written to the command
register, there's an ASSERT(!rom_only) just before the deferred write
of the command register in modify_decoding.
Thanks, Roger.
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next prev parent reply other threads:[~2018-11-16 14:32 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 11:57 [PATCH v4 0/5] x86/pvh: fix fixes for PVH Dom0 Roger Pau Monne
2018-11-14 11:57 ` [PATCH v4 1/5] vpci: fix updating the command register Roger Pau Monne
2018-11-16 12:00 ` Jan Beulich
2018-11-16 14:32 ` Roger Pau Monné [this message]
2018-11-19 8:26 ` Jan Beulich
2018-11-19 11:09 ` Roger Pau Monné
2018-11-19 11:31 ` Jan Beulich
2018-11-14 11:57 ` [PATCH v4 2/5] vpci: fix deferral of long operations Roger Pau Monne
2018-11-14 12:08 ` Paul Durrant
2018-11-16 12:11 ` Jan Beulich
2018-11-16 14:57 ` Roger Pau Monné
2018-11-19 8:27 ` Jan Beulich
2018-11-14 11:57 ` [PATCH v4 3/5] vpci/msix: carve p2m hole for MSIX MMIO regions Roger Pau Monne
2018-11-19 14:56 ` Jan Beulich
2018-11-20 14:35 ` Roger Pau Monné
2018-11-14 11:57 ` [PATCH v4 4/5] amd/iommu: assign iommu devices to Xen Roger Pau Monne
2018-11-14 12:33 ` Andrew Cooper
2018-11-14 13:53 ` Jan Beulich
2018-11-14 16:09 ` Roger Pau Monné
2018-11-15 15:34 ` Jan Beulich
2018-11-15 16:00 ` Roger Pau Monné
2018-11-14 11:57 ` [PATCH v4 5/5] amd/iommu: skip bridge devices when updating IOMMU page tables Roger Pau Monne
2018-11-15 15:40 ` Jan Beulich
2018-11-15 15:48 ` Roger Pau Monné
2018-11-15 16:13 ` Jan Beulich
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