From: Andre Przywara <andre.przywara@linaro.org>
To: Julien Grall <julien.grall@arm.com>,
Stefano Stabellini <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH 39/57] ARM: new VGIC: Add ACTIVE registers handlers
Date: Tue, 13 Mar 2018 17:34:36 +0000 [thread overview]
Message-ID: <31eca462-7be4-ef76-9ef3-927efb4d5d9f@linaro.org> (raw)
In-Reply-To: <ff733893-a7f7-b761-4b9d-22db2d316e66@arm.com>
Hi,
On 13/03/18 17:14, Julien Grall wrote:
> Hi Andre,
>
> On 13/03/18 17:02, Andre Przywara wrote:
>> On 08/03/18 15:39, Julien Grall wrote:
>>> On 05/03/18 16:03, Andre Przywara wrote:
>>>> +/*
>>>> + * We don't actually support clearing the active state of an IRQ
>>>> (yet).
>>>> + * However there is a chance that most guests use this for
>>>> initialization.
>>>> + * We check whether this MMIO access would actually affect any active
>>>> IRQ,
>>>> + * and only print our warning in this case. So clearing already
>>>> non-active
>>>> + * IRQs would not be moaned about in the logs.
>>>> + */
>>>> +void vgic_mmio_write_cactive(struct vcpu *vcpu,
>>>> + paddr_t addr, unsigned int len,
>>>> + unsigned long val)
>>>> +{
>>>> + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1);
>>>> + unsigned int i;
>>>> + bool bail_out = false;
>>>> +
>>>> + for_each_set_bit( i, &val, len * 8 )
>>>> + {
>>>> + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid
>>>> + i);
>>>> +
>>>> + /*
>>>> + * If we know that the IRQ is active or we can't be sure about
>>>> + * it (because it is currently in a CPU), log the not properly
>>>> + * emulated MMIO access.
>>>> + */
>>>> + if ( irq->active || irq->vcpu )
>>>> + {
>>>> + gdprintk(XENLOG_ERR,
>>>> + "%pv: vGICD: IRQ%d: clearing active state not
>>>> supported\n",
>>>
>>> s/%d/%u/
>>>
>>>> + vcpu, irq->intid);
>>>
>>> gdprintk will always print the vCPU. Thought it is the current which
>>> might be different from vcpu (mostly in the re-dist case).
>>
>> Ah, thanks. I always get confused about what which version of *printk
>> does.
>>
>>> So I would use dprintk(XENLOG_G_ERR, "%pv: ..."). I would even be tempt
>>> to use printk(....) so we can spot potential issue on non-debug build.
>>
>> Well, in the true spirit of Xen paranoia ;-) I wanted to avoid a guest
>> spamming the console.
>
> The guests messages are rate limited.
Ah ...
>> And in the end there is nothing a administrator
>> could really do about it. In my experience those messages tend to really
>> scare users ("I could boot Dom0 but I see those error messages ....").
>
> Xen message are not only here for the administrator, they are also here
> to help for the developer to get log to dissect.
Sure, see below ...
> I think that particular message should be printed in non-debug build
> because if the interrupt was active and can't clear it. Then something
> will go wrong later on.
Fair enough, if it's rate limited ...
>>>> + bail_out = true;
>>>
>>> I admit the bailout is a bit weird here. You would only print the
>>> warning for the first activated IRQ and give the impression it is fine
>>> for the rest. So maybe you want to drop IRQ%d?
>>
>> For the above reasons I wanted to keep them concise, so that we see that
>> the issue has happened, but avoid getting tons of error messages about
>> the same problem (as this may affect up to 32 IRQs).
>> But for debugging it might be good to know which IRQ was affected. I see
>> two use cases for a guest:
>> - (De-)activating a single IRQ: we get one message and know which IRQ it
>> was, so an admin can chase this down to a certain device (driver).
>> - (De-)activating *every* IRQ in this range (~0): we still get one
>> message per 32 IRQs, but can see whether it covers SPIs only (IRQ>=32)
>> and which ones.
>>
>> So what about a compromise: I use dprintk(XENLOG_G_ERR, "%pv ...), print
>> the (first) IRQ and the *value* to be written. So a knowledgeable admin
>> can tell whether it's a single IRQ or a "clear/set-all" case. That
>> should also give enough info for debugging, but keeps it short.
>
> I can't see how a knowledgeable admin will be able to know that IRQ 2 is
> active with just the register value.
Well, I was assuming that a really knowledgeable admin would somehow
forward the error message either to the ML or at least to $search_engine.
...
>> Does that sound OK?
>
> I would still prefer the one per IRQ and using printk(XENLOG_G_*).
I really don't think one per IRQ is too useful. A developer however can
easily deal with "IRQ45, value: 0x00802000" from a log. And can deduce
from there that it's about IRQ45 and IRQ55. Following the example above
you would either see one "IRQ32, value: 0xffffffff" or "IRQ 45, value:
0x00002000".
That looks like a good compromise between readability (having the IRQ
number for admins) and brevity.
I changed it now to output:
%pv: vGICD: clearing active state not supported (IRQ%u, value: 0x%08lx)
> I don't much care about the spam, see why above.
Having them on the console between Dom0 messages is really scary, but
not helpful if it's *more* than one. Since it's a known limitation of
the VGIC emulation, not a real "error" in that sense.
Cheers,
Andre.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2018-03-13 17:34 UTC|newest]
Thread overview: 146+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-05 16:03 [PATCH 00/57] New VGIC(-v2) implementation Andre Przywara
2018-03-05 16:03 ` [PATCH 01/57] tools: ARM: vGICv3: Avoid inserting optional DT properties Andre Przywara
2018-03-05 16:39 ` Julien Grall
2018-03-05 17:18 ` Wei Liu
2018-03-06 11:16 ` Julien Grall
2018-03-05 16:03 ` [PATCH 02/57] ARM: vGICv3: clarify on GUEST_GICV3_RDIST_REGIONS symbol Andre Przywara
2018-03-05 16:40 ` Julien Grall
2018-03-05 16:03 ` [PATCH 03/57] ARM: GICv3: use hardware GICv3 redistributor values for Dom0 Andre Przywara
2018-03-05 16:44 ` Julien Grall
2018-03-05 16:03 ` [PATCH 04/57] ARM: GICv3: simplify GICv3 redistributor stride handling Andre Przywara
2018-03-05 17:08 ` Julien Grall
2018-03-06 13:49 ` Julien Grall
2018-03-08 12:40 ` Andre Przywara
2018-03-08 15:29 ` Julien Grall
2018-03-05 16:03 ` [PATCH 05/57] ARM: vGICv3: always use architected redist stride Andre Przywara
2018-03-05 16:03 ` [PATCH 06/57] ARM: vGICv3: remove rdist_stride from VGIC structure Andre Przywara
2018-03-05 16:03 ` [PATCH 07/57] ARM: VGIC: rename gic_inject() and gic_clear_lrs() Andre Przywara
2018-03-05 17:09 ` Julien Grall
2018-03-05 16:03 ` [PATCH 08/57] ARM: VGIC: Move gic_remove_from_lr_pending() prototype Andre Przywara
2018-03-05 16:03 ` [PATCH 09/57] ARM: VGIC: Move domain_max_vcpus() to be VGIC specific Andre Przywara
2018-03-05 17:14 ` Julien Grall
2018-03-05 16:03 ` [PATCH 10/57] ARM: VGIC: rename gic_event_needs_delivery() Andre Przywara
2018-03-06 11:46 ` Julien Grall
2018-03-05 16:03 ` [PATCH 11/57] ARM: VGIC: change to level-IRQ compatible IRQ injection interface Andre Przywara
2018-03-06 11:53 ` Julien Grall
2018-03-05 16:03 ` [PATCH 12/57] ARM: VGIC: carve out struct vgic_cpu and struct vgic_dist Andre Przywara
2018-03-06 11:56 ` Julien Grall
2018-03-05 16:03 ` [PATCH 13/57] ARM: VGIC: reorder prototypes in vgic.h Andre Przywara
2018-03-05 16:03 ` [PATCH 14/57] ARM: VGIC: Introduce gic_get_nr_lrs() Andre Przywara
2018-03-06 14:02 ` Julien Grall
2018-03-05 16:03 ` [PATCH 15/57] ARM: GICv2: Extend and adjust register definitions Andre Przywara
2018-03-06 14:12 ` Julien Grall
2018-03-05 16:03 ` [PATCH 16/57] ARM: GICv3: rename HYP interface definitions to use ICH_ prefix Andre Przywara
2018-03-06 15:12 ` Julien Grall
2018-03-05 16:03 ` [PATCH 17/57] ARM: Introduce kick_vcpu() Andre Przywara
2018-03-06 15:21 ` Julien Grall
2018-03-05 16:03 ` [PATCH 18/57] ARM: GICv2: introduce gicv2_poke_irq() Andre Przywara
2018-03-06 15:23 ` Julien Grall
2018-03-06 15:25 ` Julien Grall
2018-03-05 16:03 ` [PATCH 19/57] ARM: GICv3: poke_irq: make RWP optional Andre Przywara
2018-03-06 15:37 ` Julien Grall
2018-03-05 16:03 ` [PATCH 20/57] ARM: GICv2: fix GICH_V2_LR definitions Andre Przywara
2018-03-06 15:46 ` Julien Grall
2018-03-06 15:58 ` Andre Przywara
2018-03-06 16:18 ` Julien Grall
2018-03-05 16:03 ` [PATCH 21/57] ARM: GICv2: extend LR read/write functions to cover EOI and source Andre Przywara
2018-03-06 16:06 ` Julien Grall
2018-03-08 16:25 ` Andre Przywara
2018-03-08 16:41 ` Julien Grall
2018-03-08 16:59 ` Julien Grall
2018-03-05 16:03 ` [PATCH 22/57] ARM: GIC: Allow tweaking the active and pending state of an IRQ Andre Przywara
2018-03-06 16:38 ` Julien Grall
2018-03-05 16:03 ` [PATCH 23/57] ARM: GIC: allow reading pending state of a hardware IRQ Andre Przywara
2018-03-06 16:57 ` Julien Grall
2018-03-05 16:03 ` [PATCH 24/57] ARM: timer: Handle level triggered IRQs correctly Andre Przywara
2018-03-06 17:15 ` Julien Grall
2018-03-06 17:20 ` Julien Grall
2018-03-05 16:03 ` [PATCH 25/57] ARM: evtchn: " Andre Przywara
2018-03-05 16:03 ` [PATCH 26/57] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available Andre Przywara
2018-03-06 17:23 ` Julien Grall
2018-03-05 16:03 ` [PATCH 27/57] ARM: new VGIC: Add data structure definitions Andre Przywara
2018-03-06 17:46 ` Julien Grall
2018-03-06 18:01 ` Andre Przywara
2018-03-07 10:45 ` Julien Grall
2018-03-05 16:03 ` [PATCH 28/57] ARM: new VGIC: Add acccessor to new struct vgic_irq instance Andre Przywara
2018-03-06 18:13 ` Julien Grall
2018-03-19 17:32 ` Andre Przywara
2018-03-19 21:53 ` Julien Grall
2018-03-20 10:58 ` Andre Przywara
2018-03-20 11:07 ` Julien Grall
2018-03-05 16:03 ` [PATCH 29/57] ARM: new VGIC: Implement virtual IRQ injection Andre Przywara
2018-03-07 11:02 ` Julien Grall
2018-03-07 11:22 ` Andre Przywara
2018-03-07 11:41 ` Julien Grall
2018-03-05 16:03 ` [PATCH 30/57] ARM: new VGIC: Add IRQ sorting Andre Przywara
2018-03-07 11:06 ` Julien Grall
2018-03-05 16:03 ` [PATCH 31/57] ARM: new VGIC: Add IRQ sync/flush framework Andre Przywara
2018-03-07 11:47 ` Julien Grall
2018-03-07 12:20 ` Andre Przywara
2018-03-05 16:03 ` [PATCH 32/57] ARM: new VGIC: Add GICv2 world switch backend Andre Przywara
2018-03-07 12:10 ` Julien Grall
2018-03-07 12:31 ` Andre Przywara
2018-03-05 16:03 ` [PATCH 33/57] ARM: new VGIC: Implement vgic_vcpu_pending_irq Andre Przywara
2018-03-05 16:03 ` [PATCH 34/57] ARM: new VGIC: Add MMIO handling framework Andre Przywara
2018-03-05 16:56 ` [FIXUP] replace LOG_2 with ilog2 Andre Przywara
2018-03-07 14:54 ` [PATCH 34/57] ARM: new VGIC: Add MMIO handling framework Julien Grall
2018-03-05 16:03 ` [PATCH 35/57] ARM: new VGIC: Add GICv2 " Andre Przywara
2018-03-07 15:00 ` Julien Grall
2018-03-05 16:03 ` [PATCH 36/57] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers Andre Przywara
2018-03-07 16:48 ` Julien Grall
2018-03-05 16:03 ` [PATCH 37/57] ARM: new VGIC: Add ENABLE registers handlers Andre Przywara
2018-03-07 17:01 ` Julien Grall
2018-03-07 18:20 ` Andre Przywara
2018-03-07 18:33 ` Julien Grall
2018-03-05 16:03 ` [PATCH 38/57] ARM: new VGIC: Add PENDING " Andre Przywara
2018-03-07 17:21 ` Julien Grall
2018-03-05 16:03 ` [PATCH 39/57] ARM: new VGIC: Add ACTIVE " Andre Przywara
2018-03-08 15:39 ` Julien Grall
2018-03-13 17:02 ` Andre Przywara
2018-03-13 17:14 ` Julien Grall
2018-03-13 17:16 ` Julien Grall
2018-03-13 17:34 ` Andre Przywara [this message]
2018-03-13 17:42 ` Julien Grall
2018-03-14 14:30 ` Andre Przywara
2018-03-14 14:40 ` Julien Grall
2018-03-05 16:03 ` [PATCH 40/57] ARM: new VGIC: Add PRIORITY " Andre Przywara
2018-03-08 15:48 ` Julien Grall
2018-03-08 16:21 ` Andre Przywara
2018-03-08 16:25 ` Julien Grall
2018-03-05 16:03 ` [PATCH 41/57] ARM: new VGIC: Add CONFIG " Andre Przywara
2018-03-08 16:12 ` Julien Grall
2018-03-05 16:04 ` [PATCH 42/57] ARM: new VGIC: Add TARGET " Andre Przywara
2018-03-08 16:18 ` Julien Grall
2018-03-08 16:30 ` Andre Przywara
2018-03-05 16:04 ` [PATCH 43/57] ARM: new VGIC: Add SGIR register handler Andre Przywara
2018-03-08 16:30 ` Julien Grall
2018-03-05 16:04 ` [PATCH 44/57] ARM: new VGIC: Add SGIPENDR register handlers Andre Przywara
2018-03-08 16:36 ` Julien Grall
2018-03-05 16:04 ` [PATCH 45/57] ARM: new VGIC: Handle hardware mapped IRQs Andre Przywara
2018-03-09 17:27 ` Julien Grall
2018-03-05 16:04 ` [PATCH 46/57] ARM: new VGIC: Add event channel IRQ handling Andre Przywara
2018-03-09 17:40 ` Julien Grall
2018-03-05 16:04 ` [PATCH 47/57] ARM: new VGIC: Handle virtual IRQ allocation/reservation Andre Przywara
2018-03-09 17:52 ` Julien Grall
2018-03-05 16:04 ` [PATCH 48/57] ARM: new VGIC: Dump virtual IRQ info Andre Przywara
2018-03-09 17:53 ` Julien Grall
2018-03-05 16:04 ` [PATCH 49/57] ARM: new VGIC: provide system register emulation stub Andre Przywara
2018-03-09 17:53 ` Julien Grall
2018-03-05 16:04 ` [PATCH 50/57] ARM: new VGIC: Implement arch_move_irqs() Andre Przywara
2018-03-09 17:55 ` Julien Grall
2018-03-05 16:04 ` [PATCH 51/57] ARM: new VGIC: Add preliminary stub implementation Andre Przywara
2018-03-09 18:18 ` Julien Grall
2018-03-13 15:55 ` Andre Przywara
2018-03-14 13:29 ` Julien Grall
2018-03-05 16:04 ` [PATCH 52/57] ARM: new VGIC: vgic-init: register VGIC Andre Przywara
2018-03-05 16:04 ` [PATCH 53/57] ARM: new VGIC: vgic-init: implement vgic_init Andre Przywara
2018-03-09 18:24 ` Julien Grall
2018-03-05 16:04 ` [PATCH 54/57] ARM: new VGIC: vgic-init: implement map_resources Andre Przywara
2018-03-09 18:27 ` Julien Grall
2018-03-05 16:04 ` [PATCH 55/57] ARM: new VGIC: Add vgic_v2_enable Andre Przywara
2018-03-09 18:29 ` Julien Grall
2018-03-05 16:04 ` [PATCH 56/57] ARM: allocate two pages for struct vcpu Andre Przywara
2018-03-09 18:30 ` Julien Grall
2018-03-05 16:04 ` [PATCH 57/57] ARM: VGIC: wire new VGIC(-v2) files into Xen build system Andre Przywara
2018-03-09 18:34 ` Julien Grall
2018-03-05 17:34 ` [PATCH 00/57] New VGIC(-v2) implementation Andre Przywara
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=31eca462-7be4-ef76-9ef3-927efb4d5d9f@linaro.org \
--to=andre.przywara@linaro.org \
--cc=julien.grall@arm.com \
--cc=sstabellini@kernel.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).